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Lecture 7 Chap 9: Registers

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Title: Lecture 7 Chap 9: Registers


1
Lecture 7Chap 9 Registers
Instructors Fu-Chiung Cheng (???) Associate
Professor Computer Science Engineering Tatung
University
2
Registers
  • registers a flip-flop or a bank of flip-flops
    with comon
  • control
  • The register is contained within the process
    statement.
  • Register match the template
  • wait until ckevent and ck 1
  • Example

3
library ieee use ieee.std_logic_1164.all entity
Dtype is port(d, ck in std_logic q out
std_logic) end architecture behavior of Dtype
is begin process begin wait until
ckevent and ck1 q lt d end process end
4
Registers simulation model
  • wait statement syntax
  • wait on sensitivity-list until condition
  • Thus
  • wait until ckevent and ck1
  • wait on ck until ckevent and ck1
  • Operation
  • A. the wait statement is activated by an
    event.
  • B. the until condition is tested
  • true process execution
  • false wait statement is deactivated.
  • (process remain suspended)

5
Registers redundancy?
  • The following example
  • wait until ckevent and ck1
  • wait on ck until ckevent and ck1
  • the process will be executed once when
  • ck 1 and ck has a transition (the rising
    edge on ck )
  • Redundancy
  • wait on ck until ckevent and ck1
  • ckevent and on ck (ck is in the
    sensitivity list)
  • means the same thing.
  • However, synthesis tools need to match this
    pattern
  • (register template) to recognize a register
    process.

6
Registers synthesis model
  • Hardware implementation an edge-triggered
    register
  • register process a block of combinational
    logic(CL)
  • registers on every output of the CL
  • All signal assignments in a registered process
    result in
  • in registers on those target signals.
  • Note that a latched process can have both
    latched and
  • combinational outputs.

7
Registers
-- compare to this process begin wait on a,
b z lt a and b end process
  • register process

process begin wait until ckevent and
ck1 z lt a and b end process
8
Register Templates basic
  • Basic Template
  • A implicit on clause
  • process
  • begin
  • wait until ckevent and ck1
  • q lt d
  • end process
  • B. explicit on clause
  • wait on ck until ckevent and ck1

9
Register Templates short
  • Short Template
  • (the most compact form of registered process)
  • process
  • begin
  • wait until ck1
  • q lt d
  • end process
  • Note that the least likely to be recognized by
    all
  • synthesisers.
  • Explicit on clause
  • wait on ck until ck1

10
Register Templates if statement
  • if statement Template
  • process
  • begin
  • wait on ck
  • if ckevent and ck1 then
  • q lt d
  • end if
  • end process
  • ckevent may be removed.
  • if ck1 then
  • asynchronous reset (see section 9.8).

11
Register Templates sensitivity list
  • sensitivity list Template
  • process (ck)
  • begin
  • if ckevent and ck1 then
  • q lt d
  • end if
  • end process
  • ckevent may be removed.
  • if ck1 then

wait on ck
12
Register active edge
  • falling-edge sensitivity register
  • process
  • begin
  • wait until ck0
  • q lt d
  • end process
  • testing the rising or falling edge
  • rising edge 0 --gt 1 but how about x --gt 1?
  • Rising-edge trigger process
  • wait until ckevent and ck1 and
    cklast_value0
  • Check synthesiser documentation.

13
Register active edge
  • All signals are initialized with the leftmost
    value of
  • the type.
  • Signal ck std_logic
  • The leftmost value of std_logic is U.
  • This may cause false triggering of registers
  • Preventing false triggering by initialization
  • Signal ck std_logic0
  • Signal ck std_logic1
  • Note that std_logic_1164 defines two functions
  • wait on rising_edge(ck)
  • wait on falling_edge(ck)
  • Not all tool support these functions.

14
Registers of other types
  • signal being registered can be
  • A. 1-bit signal
  • B. integer (Ex. Counter)
  • C. enumeration (Ex. State machines)
  • D. array type (Ex. Buses)
  • E. record type (Ex buses split into fields.)
  • Example

15
library ieee use ieee.std_logic_1164.all,
ieee.numeric_std.all entity Dtype is port(d
in signed(7 downto 0) ck in std_logic q
out signed(7 downto 0)) end architecture
behavior of Dtype is begin process
begin wait on ck until ck1 q lt d --
8-bit register end process end
16
Registers of other types
  • any number of signals can be registered in the
    same
  • registered process.
  • Example
  • process
  • begin
  • wait on ck until ck1
  • q0 lt d0
  • q1 lt d1
  • q2 lt d2
  • end process

17
Clock types
  • So far all the examples have used a clock which
    is
  • of type std_logic.
  • Other logic types are OK for clock signal
  • A. bit
  • B. boolean

18
Gated Registers
  • So far all the registers have been ungated.
  • In practice, it is very rare for a register to
    be ungated.
  • A. clock gating -- in general not OK, rare
  • B. data gating

19
Clock Gating
  • In clock gating the clock signal is switched on
    or off
  • by some other control signals. -- save power
  • Clock gating is sometimes used in hand-crafted
    design.
  • It is rarely used and considered bad practice to
    use
  • clock gating in synthesisable design.
  • Two reasons
  • A. Testing (synchronous design) scan paths
    with
  • built-in test patten generation to give a
    complete test.
  • Scan techniques require directly control
    the clocks.
  • B. Glitches logic synthesis for logic
    minimization can
  • not guarantee glitch-free logic.
  • Glitches in the control signals would be
    disastrous.

20
Glitches (Hazards)
  • Static hazards
  • Dynamic hazards

Static 0 hazard Static 1 hazard
1
O
1
1
O
O
21
Glitches (Hazards)
22
Clock gating
  • Clock gating is often used in low-power
    circuits.
  • Clock gating is used to effectively disable a
    register
  • or a register bank.
  • If clock gating is used, User has to check that
  • synthesized clock circuits are safe.
  • Example

23
library ieee use ieee.std_logic_1164.all entity
GDtype is port(d, en, ck in std_logic q
out std_logic) end architecture behavior of
GDtype is signal cken std_logic begin
cken lt ck when en 1 else 1 -- clock
gating process begin wait until
ckenevent and cken1 q lt d end
process end
24
Data gating
  • Data gating controls the data input of the
    register.
  • Hardware implementation multiplexer
  • Example

25
library ieee use ieee.std_logic_1164.all entity
DGDtype is port(d, en, ck in std_logic q
out std_logic) end architecture behavior of
DGDtype is begin process begin wait
until ckevent and ck1 if en 1 then --
data q lt d -- gating end if end
process end
26
Data gating
  • common pitfall dont combine if statements
  • if ckevent and ck1 then
  • if en 1 then -- data gating
  • q lt d
  • end if
  • endif
  • Not OK (register template ??)
  • if ckevent and ck1 and en 1 then
  • q lt d
  • endif

27
Resettable Registers
  • Register reset Asynchronous and synchronous
  • Asynchronous resets
  • A. override the clock and act immediately to
    change the
  • value of the register.
  • B. global system-level resets enforced from
    off-chip
  • C. sensitive to glitches (asynchronous reset
    controls
  • are in effect always.)
  • Synchronous resets
  • A. take effect on the active edge of the clock
  • B. insensitive to glitches

28
Asynchronous Reset
  • Asynchronous resets require special register
    template
  • Many different ways to write models that act
    like
  • asynchronous resets during simulation
  • Only those that conform to the templates will be
  • synthesisable.
  • The templates vary from synthesizer to
    synthesizer.
  • Example

29
Asynchronous Reset
  • An asynchronous reset example
  • process(ck,rst)
  • begin
  • if rst 1 then
  • q lt0
  • elsif ckevent and ck1 then
  • q lt d
  • end if
  • end

30
Asynchronous Reset
  • Some synthesizer requires attributed entity to
    declare
  • an asynchronous reset example
  • library ieee
  • use ieee.std_logic_1164.all
  • library synthesis
  • use synthesis.attributes.all
  • entity RDtype is
  • port(d, rst, ck in std_logic q out
    std_logic)
  • attribute signal_kind of ck signal is clock
  • attribute signal_kind of rst signal is
    set_reset
  • end

31
Asynchronous Reset
  • Reset value can be any constant value.
  • process(ck,rst)
  • begin
  • if rst 1 then
  • q lt to_unsigned(10, qlength)
  • elsif ckevent and ck1 then
  • q lt d
  • end if
  • end

32
Asynchronous Set and Reset
  • Asynchronous set and reset controls may not be
  • synthesisable.
  • process(ck,rst, set)
  • begin
  • if rst 1 then
  • q lt 0
  • elsif set 1 then
  • q lt 1
  • else ckevent and ck1 then
  • q lt d
  • end if
  • end

33
Resettable Counter
  • module-16 counter
  • signal ck, rst std_logic
  • signal q unsigned( 3 downto 0)
  • .
  • process(ck,rst)
  • begin
  • if rst 1 then
  • count lt to_unsigned(0, countlength)
  • elsif ckevent and ck1 then
  • count lt count 1
  • end if
  • end

34
Synchronous Reset
signal d, ck, rst std_logic signal q
std_logic . process begin wait
until ckevent and ck1 if rst 1 then
q lt 0 else q lt d end
if end
35
signal d unsigned(2 downto 0) signal ck, rst
in std_logic signal q out unsigned(2 downto
0) . process begin wait until
ckevent and ck1 if rst 1 then q lt
to_unsigned(5, qlength) else q lt
d end if end
36
Synchronous Resettable Counter
signal ck, rst std_logic signal q unsigned(3
downto 0) . process (ck) begin if
ckevent and ck1 then if rst 1
then count lt to_unsigned(0,
countlength) else count lt
count1 endif end if end
37
Simulation model of Asynchronous Reset
  • Asynchronous reset behavior is more complex.
  • process (ck, rst)
  • begin
  • if rst1 then
  • q lt 0
  • elsif ckevent and ck1 then
  • q lt d
  • end if
  • end
  • two signals, ck (the clock signal) and rst
    (asynchronous
  • reset signal) are in the sensitivity list.

38
Simulation model of Asynchronous Reset
  • if rst goes high, q will be reset to zero.
  • If ck goes high, q will be set to d.
  • If both rst and ck go high then reset signal
    overrides the
  • clock signal
  • Note that asynchronous reset acts as a level
    sensitive
  • control signal. The reset is activated
    immediately and is
  • not synchronized with the clock.
  • VHDL synthesizers recognize an asynchronous
    reset by
  • matching an asynchronous reset template.

39
Asynchronous Reset Templates
  • Asynchronous reset templates
  • A. sensitivity-list template
  • process (ck, rst)
  • begin
  • if rst1 then
  • q lt 0
  • elsif ckevent and ck1 then
  • q lt d
  • end if
  • end

40
Asynchronous Reset Templates
  • Asynchronous reset templates
  • B. if-statement template
  • process
  • begin
  • wait on ck, rst
  • if rst1 then
  • q lt 0
  • elsif ckevent and ck1 then
  • q lt d
  • end if
  • end

41
Registered Variables
process variable count unsigned(7 downto
0) begin wait until ckevent and ck1
if rst 1 then count to_unsigned(0,
countlength) else count
count1 end if result lt count -- two
registers are created end
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