DEVICE OPTIMISATION AND HIL PARAMETERISATION

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DEVICE OPTIMISATION AND HIL PARAMETERISATION
UNIVERSITY OF CAMBRIDGE
Patrick Palmer, Angus Bryant, Andrew Bradley
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Complex System Modelling
Systems are hierarchical, e.g.
Devices
Circuit
Control Loops
High-level system
IGBTs Diodes
Process Control
Inverters
Drives

• Lack of integration ? leads to
• - independent simulation
• - independent optimisation
• Different simulators for each part.

Benefits to be gained from integrating these
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Device and Circuit Modelling

• Device simulation
• Simplifies circuit to basic behaviour
• Concentrates on device physics
• Detailed simulation, hence time-consuming
• Circuit simulation
• Uses simple device models
• ? can simulate rest of circuit feasibly
• Device behaviour not as accurate
• ? important phenomena may be missed

Need for - quicker device modelling - more
accurate circuit modelling
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Combined Device and Circuit Modelling

• VTB offers an integrated simulation environment.
• The visualisation - simulation environment allows
  effective scenario testing.
• Detailed models may be included keeping system
  complexity in perspective.

Detailed models are required which interface to
VTB
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Device Simulation

• Finite element (e.g. ATLAS, Medici)
• Whole device modelled
• Fine mesh ? high accuracy, slow execution speed
• Lumped charge (e.g. PSpice)
• A few (lt10) points through device modelled ?
  lower accuracy
• High execution speed ? suitable for circuit
  simulation
• Fourier model
• Low-doped base region modelled
• Ambipolar carrier storage region modelled using
  Fourier series
• Depletion layers assumed ideal
• High accuracy, high speed
• Agrees well with detailed simulation and
  experimental results
• Previously used ESACAP, PSpice
• Difficult to interface to other software

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Why Simulink?

• Part of the MATLAB environment
• Allows extended features
• - optimisation
• - advanced data analysis

• Device models in Simulink
• Block-based Level 3 models
• - small number of discrete equations
• - hierarchical structure allows simple modelling

Include the immediate external circuit in Simulink
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System Model

• Simple chopper circuit
• Most inverter circuits can be reduced
• to this model
• Uses both IGBT and diode models
• R0, L0 load
• RS, CS snubber
• LS stray inductance
• VGG, RG, LG gate drive

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Device Physics
PN-N diode

• Boundary conditions
• - Depletion layer width
• - Injection currents from
• P/N regions
• - Anode current
• Device outputs
• - Depletion layer voltages
• - Base resistance
• - P-N junction voltage
• Applications
• - Diode model extended
• - Can be used to model
• IGBTs
• Bipolar transistors
• Thyristors

N-
Depletion layer 1
Depletion layer 2
P
N
Carrier storage region
Electric field E
Carrier conc. p,n
Carrier Storage Region
Ip1
Ip2
In1
In2
p(x,t)
Depletion Layer 1
Depletion Layer 2
x
x1
x2
WB
0
E(x,t)
E(x,t)
Vd2
Vd1
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Distributed Fourier Method

• Central carrier storage region
• - Represents carrier density as Fourier
  series in space
• - Allows reasonable accuracy with few data
  points (i.e. length of Fourier series)
• - Boundary conditions
• - width of region
• - electron and hole currents
• - Boundary conditions and Fourier terms vary
  with time
• ? Transient behaviour
• Boundary conditions
• - Depletion layers
• - widths from zero-crossing points of carrier
  density
• - implemented by simple high-gain feedback from
  boundary densities
• - Hole and electron currents
• - injection from highly-doped region depends on
  boundary densities
• - anode current is total at each boundary

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Simulation Issues

• Convergence aids
• - snubber across diode
• - upper frequency limits on differentiators
• Model used matrix and vector functions for
  compact implementation of fourier series
• ode15s solver (similar to Gears method) used
  since system is stiff
• ? variable time-step

A variable time step is essential!
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Diode Model

• Simple carrier storage model both boundaries
  mobile
• Base resistance external to diode to aid
  simulation

Emitter recombination currents
p-n-junction voltage
Carrier storage region
Depletion layers
Base resistance (ohmic)
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IGBT Model

• Only one mobile boundary (as only one
  reverse-biased depletion layer)
• MOSFET model required careful implementation
• Gate behaviour part of IGBT model

MOSFET conduction
Base resistance
Miller capacitance
Carrier storage region
Depletion layer
Gate circuit
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Device Optimisation Background

• Optimisation minimises an objective function,
  e.g.
• - Diode power dissipation
• - IGBT power dissipation
• - Turn-on time
• - Turn-off time
• - Any combination of the above
• Objective function is a non-analytic function of
  the parameters, e.g. - Base width, WB
• - Carrier lifetime, t
• - Stray inductance, LS
• These are varied to minimise the objective
  function

MATLAB calls the simulation, evaluates the
objective function and handles the optimisation.
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Optimisation Algorithm

• Direct search algorithm, based on Hooke Jeeves
• - Pattern moves used to speed up search
• - Avoids becoming stuck in local minima tabu
  search (recently-
• visited points not re-visited in near future)

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Simulation Results Summary

• Previous simulation provides initial conditions
  for this simulation

Run time for each simulation is 5-10 seconds
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Simulation Results Switching Detail

• IGBT switch-on
• Diode switch-off
• Note diode recovery and gate voltage plateau

• IGBT switch-off
• Diode switch-on
• Note gate voltage plateau and IGBT current
  tail

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Simulation Results Carrier Densities
DIODE
IGBT
Carrier density (1015 cm-3)
Carrier density (1015 cm-3)
-10 0 10 20 30 40
50 60 70 80 90 100
-10 -5 0 5
10 15 20 25
30
0 100
200
266
0
100
180
Base width (?m)
Base width (?m)

• 21 terms in Fourier series for high resolution
• Variable time-step ? switching instances
  simulated in more detail

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Optimisation Results

• Diode and IGBT optimised individually and
  together
• Circuit optimised separately

Dissipation gt 6000W
Device optimised Dissipation used for obj.
fnc.
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Optimisation Results Waveforms

• Shown for IGBT turn-on/
• diode turn-off
• Diode recovery reduced, IGBT
• voltage tail reduced
• Similar results for IGBT turn-off/
• diode turn-on

Base IGBT and diode A, WB, NB, t (based on
total power) Circuit RG, LS (based on total
power)
IGBT Gate voltage turn-on
Diode current (top) and voltage (bottom)
turn-off
IGBT current (top) and voltage (bottom) turn-on
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Optimisation Results Device Trends

• For combined IGBT/diode
  case,
• IGBT
• Area A ? Before 1.0cm2 After 0.892cm2
• Base width WB ? 266mm 114mm
• Base doping NB ? 5e13cm-3 9.4e13cm-3
• Lifetime t ? (lim) 30ms 100ms
• Diode
• Area A ? (lim) 0.3cm2 0.05cm2
• Base width WB ? (lim) 180mm 120mm
• Base doping NB ? (lim) 1e14cm-3 1e15cm-3
• Lifetime t ? 0.44ms 0.248ms
• ? Parameter increase
• ? Parameter decrease
• lim Parameter limited

Shows that performance improves if devices driven
harder (higher E-field, current density)
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Optimisation Results Circuit Trends

• Scatter plot for circuit optimisation (LS, RG)
  shows search

RG reduced greatly, LS increased slightly
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Issues in optimisation

• Simulation
• Rapid
• Accurate
• Optimisation
• Drives devices harder
• Shows interdependency
• Optimal stray inductance is not small
• Limitations
• Convergence not guaranteed for some conditions

A guide, not a substitute for experimental testing
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HIL Hardware-in-the-Loop

• Range of conditions applied
• Linked to simulation optimisation
• Applications
• Comprehensive device circuit testing
• Automatic parameterisation

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HIL Hardware-in-the-Loop

• Conditions applied according to use
• Applications
• Comprehensive device circuit testing
• Automatic parameterisation

The ultimate experimental experience!
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HIL Experimentation

• Software control
• MATLAB sends commands to Xilinx FPGA hardware to
  drive devices and circuit
• ? generates correct conditions
• Captures behaviour via LeCroy oscilloscope and
  ActiveX
• Gearing
• Assumes system (simulated) behaves as expected
  and creates the conditions for devices circuit
• Hardware cycles indefinitely until updated by
  software
• PC only measures waveforms when conditions change
• Reduced data transfer rate between PC and
  hardware

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3-phase bridge in VTB
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Hardware bridge circuit

• Bridge configuration
• only 2 legs used
• Devices under test
• (DUTs) arranged as module
• Unipolar switching
• Auxiliary leg sets up
• current
• Independent control
• of I0, duty r

Completely flexible
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Hardware Interface

• Hardware PWM
• Controlled via serial port

• LeCroy oscilloscope
• Controlled via network

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PWM Generation

• FPGA generates square
• wave
• Receives duty ratio sent via
• serial port
• Uses existing circuitry
• Gate drives connected to
• FPGA

• Hardware PWM
• Controlled via serial port

UART (serial-parallel converter)
PC Serial Port
Xilinx FPGA
Gate drives
Bridge IGBTs
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Waveform Acquisition Summary

• LeCroy oscilloscope
• - High sample rate
• - Large memory
• - Ethernet support
• - ActiveX support
• MATLAB
• - Reads scope trace
• - Controls scope via ActiveX
• - Processes data from scope

• LeCroy oscilloscope
• Controlled via network

Circuit devices
LeCroy scope
Network (ethernet)
PC running software
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Waveform Acquisition Details

• Active X interface
• - Provided by LeCroy Active DSO (installed on
  PC)
• - Simple call from MATLAB
• Create ActiveX object
• dso actserver(LeCroy.ActiveDSOCtrl.1)
• Connect to scope
• invoke(dso, MakeConnection, IP129.169.123.52
  )
• Set up timebase and voltage scales
• invoke(dso, WriteString, C1VDIV 0.5V, 1)
• invoke(dso, WriteString, TDIV 5e-6, 1)
• Read data from scope and store in array
• W invoke(dso, GetScaledWaveform, C1,
  15000, 0) V invoke(dso, GetScaledWaveform,
  C2, 15000, 0)

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Experimental Setup
FPGA, Gate Drives
LeCroy DSO
Auxiliary Circuit
DUT
Load
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Results Current

• Current varied by keeping rA constant, varying rB

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Results Pulse Width

• Current held constant by keeping rA-rB constant
  while varying rA and rB

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Results Sine Wave Cycle

• Sine wave pieced together from consecutive runs
  (gearing)

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Results Sine Wave Detail (1)

• Detail still present for zooming in

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Results Sine Wave Detail (2)

• IGBT turn-off waveforms

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Further DevelopmentSimulation, Optimisation

• Development of models
• Diode punch-through, lifetime zoning, dynamic
  avalanche
• ? finite difference
• IGBT punch-through (buffer layer), 2-D
  depletion layer at
• MOSFET end
• Condition cycling
• Cycles through range of load cases (V, I, f, r,
  T) during optimisation
• to ensure that devices can cope with all
  conditions
• See later for details
• Extension of chopper cell
• Generalise to simulate series devices and/or
  multilevel converters
• (imbricated cells/flying-capacitor)
• - Optimisation of active gate drive simple
  modelling in Simulink

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Further Development HIL

• Condition cycling
• Parameterisation
• Development of hardware flexibility
• Series connection of devices
• Multi-level connection of devices
• Combination of the two
• Further freedom of load current from supply
  voltage
• Higher voltage testing
• More advanced PWM generation in FPGA

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Condition Cycling

• Sweeps full range of conditions
• ? no stone left unturned
• Improves on typical high-power-only testing
• investigates possibly infrequent, but feasible
  conditions
• examines their effect on device and circuit
  stress
• Tests all combinations of V, I, f, r, T
• if, say, 5 levels of each ? 55 3125 conditions
• Technique used in device/circuit optimisation
• performance verificaton
• Data used in
• device/circuit performance and reliability
  evaluation
• automatic parameterisation
• Conditions can reflect typical scenarios
• sinewave PWM load current gt50 for 2/3 of time
• load cycles, e.g. hard acceleration/deceleration
  in traction

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Parameterisation

• Parameter fitting is optimisation!
• Objective function is error between simulation
  and
• measured waveforms, e.g. sum of squares
• Parameters varied to minimise error
• Can use core of device/circuit optimisation
• Basic device testing will happen as part of
  process if
• correct condition cycling is imposed
• Advantages
• Useful extension of optimisation
• Accurate models of devices developed
• Tests devices simultaneously

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Hardware Development
DUT Diode
VS2
Multilevel half-bridge (remove capacitors
for series connection)
Auxiliary circuit
I0
L0
R0
VS1
DUT IGBT

• Extend bridge to operate at higher voltages
• ? takes advantage of implicit boost conversion
• Allows greater freedom of load current from
  device voltage
• Stresses devices more
• ? high forward current, high blocking voltage
• Implement series multi-level capability
• ? investigate compromise between the two