EE272 VLSI Project Class

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EE272VLSI Project Class

• Ken Mai, Elad Alon, Francois Labonte

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Overview

• Class goal
• Learn about all aspects of chip
  design/implementation
• Design and implement a small chip of your own
  design
• Class mechanics
• Administrative issues
• Lecture topics
• Design issues
• Design flow and tools
• Design styles
• Past projects

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Class goal

• Learn about building chips, by building a small
  one
• 2K x 2K area
• 40 pins (8 taken up by Vdd, gnd, and clk)
• 0.5mm 3-metal process technology
• Complete, verified, working designs in 9 weeks
• Hard deadline 5pm March 7 (fabrication
  schedule)
• Dont go crazy (overly aggressive) with the
  design
• Not intended to be research-grade chips
• But do have a little fun
• Chips come back in Spring quarter (EE272B)
• You must test them (requirement of free
  fabrication)
• Complete CAD tool design flow
• Use many of the types of tools that are used in
  industry
• Youve seen most of the tools before

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Administrative issues

• Fill out the student info sheet
• Find a partner
• Pre-requisites
• EE271 or equivalent
• Willingness to work hard
• Group meetings
• Required 30-minute bi-weekly meetings
• Information distribution
• Webpage www.stanford.edu/class/ee272
• Newsgroup su.class.ee272a

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Workload

• Typically about 175 hours over 9 weeks
• This is a lot (average of 20 hours per week)
• More packed towards the end of the quarter

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Lecture schedule
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Design flow
Concept
HDL
Partition
Schematics
Synthesis
Datapath
Control
Place/route
Layout
Global route
Tapeout checks
Sleep
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Design flow tools

• Design
• HDL Verilog
• Schematic entry SUE
• Layout Magic
• Synthesis Synopsys
• Place/route Snake
• Verification
• Vcheck check clocking of verilog
• Rsimverilog generate irsim test vectors from
  verilog
• Checks functionality of verilog model against
  schematic/layout
• IRSIM switch level simulator
• Gemini netlist comparator
• Checks schematic against layout

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Design styles partitioning

• Partition your chip into logical/functional
  sections
• Datapath
• Fairly regular, replicated, and dense
• Custom layout
• Array structures are a special subset (e.g.
  memories)
• Ex ALU, shifters
• Control
• General, random structure
• Standard cell synthesis and place-and-route
• Ex FSM, instruction decoders

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Design styles partitioning contd

• Most chips end up looking something like this
• Ex Processors
• Some are skewed heavily towards one block or
  another
• Functional units are mostly datapath
• Memories are mostly array

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Design styles circuits

• Dont get too fancy
• Not the point of the project
• Youre restricted to a few styles
• Static CMOS
• Precharged CMOS, domino logic
• Pseudo-NMOS (in special cases)

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Design styles clocking

• Again, dont get too fancy
• Also not the point of the project
• 2-phase clocking
• Use EE271 verilog coding rules
• Verify with vcheck script
• Self-timed
• Using completion detectors (e.g. Ted Williams
  stuff)
• Self-clocked
• On-chip clock generator
• Use replica logic blocks to generate clock
• Must have bypass path to allow for off-chip clock
  source

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Past projects

• Projects generally fall into 4 categories
• Processors
• Functional units
• Memories
• Weird (e.g. game chips)
• Catalog of past projects on the web page
• Get a feel for whats doable in the time/space
  allotted
• Steal the boring stuff
• Some older links may be broken

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Final issues

• If you do not have a partner, stay after class
  and find one
• If youre unsure about the class, do NOT find a
  partner
• Please fill out the student info sheet before
  leaving