Low Power and High Speed Multi Threshold Voltage Interface Circuits

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Low Power and High Speed Multi ThresholdVoltage
Interface Circuits

• By
• Sherif A. Tawfik and Volkan Kursun
• Presented by
• Ramasamy Ethiraj

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Contents

• Introduction
• Standard Feedback-Based Level Converters
• Proposed Multi-Vth Level Converters
• Delay and Power consumption of level Converters
• - Comparison of level converters
• - The performance of level converters under
  Supply Voltage
• and Process Parameter Variations
• - Multi Vth-CMOS Technology
• CONCLUSION

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Introduction

• Scaling the supply voltage to reduce the power
• Lower supply will degrade the speed
• Multi-VDD Techniques and Conventional Level
  converters are introduced.
• Conventional Level converters will introduce DC
  current and feedback circuit (hence slow
  response)
• Multi-Vth Level converters will eliminate DC
  current and Feedback circuit.

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Standard Level Converters 1 (LC1)

• VDDL is directly connected to M3 M4 DC path.
  So high power
• Feedback circuit more delay.
• M1 M2 should be large, because VDDL is directly
  connected. Result in large capacitance and area

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Standard Level Converters 2 (LC2)

• VDDL is not directly connected to PMOS still
  some DC current
• Feedback circuit more delay.
• More device count- more delay and power
• M2 should be large, because VDDL is directly
  connected. Result in large capacitance and area

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Proposed Multi-Vth Level Converter1 (PC1)

• Vth-M2 should be more negative than VDDL VDDH to
  avoid DC current
• No feedback circuit less delay.
• less device count- less delay, area and power
• Smaller transistor sizes.

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Proposed Multi-Vth Level Converter2 (PC2)

• Vth-M2 should be more negative than VDDL VDDH to
  avoid DC current
• Multi Vth is used for M3.
• Lowest delay compare to other converters
• No feedback circuit less delay.
• Smaller transistor sizes.

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Proposed Multi-Vth Level Converter2 (PC2)

• Vth-M2 should be more negative than VDDL VDDH to
  avoid DC current
• M3,M4,C is removed for lower VDDL
• No feedback circuit less delay.
• Smaller transistor sizes.

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Simulation Setup

• 0.18um technology
• VDDH 1.8V
• Simulated for different VDDL 0.5, 1 and 1.2V
• Wn Wmin, Wp 2.5Wn
• Delay is measured between input of ID and Node2
• Power consumption measured for entire setup

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Optimum Delay and Power measurements
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Normalized to LC2
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• The performance of level converters under Supply
  Voltage and Process Parameter Variations

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Power and Delay comparison LC2 vs. PC2for
Power optimized circuit (VDDL 1.2V)
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Power and Delay comparison LC2 vs. PC1for
Power optimized circuit (VDDL 1V)
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Power and Delay comparison LC2 vs. PC1for
Power optimized circuit (VDDL 0.5V)
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Vth-M2 vs. Power and Delay
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Conclusions

• Multi-Vth level converters has up to 78 less
  delay compare to standard level converters
• 70 less power consumption
• Less Device count and size minimum Area
• Wide range of threshold voltages
• High speed and low power.

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Thank You