HIGH SPEED LINEAR DESIGN SEMINAR SWITZERLAND

1
HIGH SPEED LINEAR DESIGN SEMINARSWITZERLAND
NOVEMBER 2001

• EurIng James M. Bryant Head of European
  Applications
• ? (44) 7785-305598
• ? james.bryant_at_analog.com

2
LOW VOLTAGE, HIGH SPEEDPRECISION ANALOG CIRCUITRY
Several different factors are encouraging the use
of low voltage analog circuits- High density
(sub-micron) IC processes have low breakdown
voltages(these processes are valuable for their
higher speed and smaller size which leads to
lower cost) Battery powered equipment is more
easily designed with low supply voltages Low
supply voltage tends to result in lower power
dissipation,leading to fewer thermal problems,
slower ageing, and longer battery life
3
LOW VOLTAGE, HIGH SPEEDPRECISION ANALOG CIRCUITRY
Present sub-micron processes have breakdowns of 7
V or less There are both bipolar and CMOS
processes with these feature sizes The bipolar
processes (XFCB and others) are used to
manufacturehigh speed analog circuitry such as
amplifiers and transceivers CMOS processes make
digital circuits, but are also used to makehigh
speed and/or high performance data converters
(ADCs and DACs)and related products such as
Direct Digital Synthesis (DDS) circuits
4
LOW VOLTAGE, HIGH SPEEDPRECISION ANALOG CIRCUITRY
Present sub-micron processes have breakdowns of 7
V or less As circuit densities become higher
breakdown voltages will be even lower These
processes allow very complex circuitsto be made
very cheaply so the trend will continue Smaller
feature sizes also permit faster operation
5
LOW VOLTAGE, HIGH SPEEDPRECISION ANALOG CIRCUITRY
But low voltage analog circuits have some
problems- Reducing the supply voltage does not
reduce noise Techniques to improve headroom
affect circuit performance Low voltage circuitry
is often single supply which complicatesthe
design of circuits which work with bipolar signals
6
LOW VOLTAGE, HIGH SPEEDPRECISION ANALOG CIRCUITRY
Reducing the supply voltage does not reduce
noise Classical precision analog circuitry used
15 V supplieswhich allowed signal swings of 10
V or 20 V pk-pk Circuits operating from a modern
2.7 V supply will have a signalswing of a little
over 2 V pk-pk a 20 dB loss of dynamic
range Some users cannot tolerate
this(Professional audio designers continually
request amplifiers and converters with much
higher supply voltages!)
7
BIT SIZES FOR 2.5 V FULLSCALE CONVERTERS
VOLTAGE (10V FS) 625 mV 156 mV 39.1
mV 9.77mV 2.44 mV 610 mV 153 mV 38 mV 9.54
mV 2.38 mV 596 nV 149 nV
RESOLUTION N 2-BIT 4-BIT 6-BIT 8-BIT 10-BIT 12-BIT
14-BIT 16-BIT 18-BIT 20-BIT 22-BIT 24-BIT
ppm FS 250,000 62,500 15,625 3,906 977 244 61 15
4 1 0.24 0.06
FS 25 6.25 1.56 0.39 0.098 0.024 0.0061 0.0015
0.0004 0.0001 0.000024 0.000006
dB FS -12 -24 -36 -48 -60 -72 -84 -96 -108 -120
-132 -144
2N 4 16 64 256 1,024 4,096 16,384 65,536 262,144 1
,048,576 4,194,304 16,777,216
149nV is the Johnson Noise in a 27kHz BW of a 50
W Resistor _at_ 25C Remember 10-bits and 2.5 V FS
yields an LSB of 2.5mV, 1000ppm, or 0.1. All
other values may be calculated by powers of 2.
8
LOW VOLTAGE, HIGH SPEEDPRECISION ANALOG CIRCUITRY
Techniques to improve headroom affect circuit
performance The commonest is to make low-voltage
analog circuitry rail-rail The term rail-rail
can apply to input or output circuitry, or
both Rail-rail input stages have disadvantages
over classical types Rail-rail output stages have
disadvantages too, but minor ones
9
ISSUES WITH RAIL-RAIL INPUT STAGESCLASSICAL
BIPOLAR TRANSISTOR INPUT STAGE
VIN

• Low Offset As Low as 10mV
• Low Offset Drift As Low as 0.1mV/ºC
• Temperature Stable Ibias
• Well-Matched Bias Currents
• Low Voltage Noise As Low as 1nV/ÖHz

• High Bias Currents 50nA - 10mA
• (Except Super-Beta 50pA - 5nA, More Complex and
  Slower)
• Medium Current Noise 1pA/ÖHz

10
ISSUES WITH RAIL-RAIL INPUT STAGES BIAS-CURRENT
COMPENSATED BIPOLAR INPUT
VIN

• Low Offset Voltage As Low as 10mV
• Low Offset Drift As Low as 0.1mV/ºC
• Temperature Stable Ibias
• Low Bias Currents lt0.5 - 10nA
• Low Voltage Noise As Low as 1nV/ÖHz

• Poor Bias Current Match (Currents May Even Flow
  in Opposite Directions)
• High Current Noise
• Not Very Useful at HF

11
ISSUES WITH RAIL-RAIL INPUT STAGES JUNCTION
FIELD EFFECT TRANSISTOR (JFET) INPUTOP AMP STAGE
SHOWING OFFSET AND DRIFT TRIMS
1 DRIFT TRIM
2 OFFSET TRIM

• Offset as Low as 50mV
• Offset TC 5mV/C
• Low Current Noise
• Bias Current as Low as 20fA

• Ib doubles every 10C
• Tradeoff Between Voltage Noise and Input
  Capacitances

12
RAIL-TO-RAIL INPUT STAGES

• Require two long-tailed pairs with inputs in
  parallel
• Vos, Ib, and CMRR vary over their common mode
  range
• An on-chip inverter may be used to generate a
  power rail outside the external power supplies,
  but this adds noise.
• It is often possible to use a single-supply op
  ampwhich allows the input signal to go to only
  one ofthe rails (usually ground).

One with NPN BJTs (or P-Channel FETs) One with
PNP BJTs (or N-Channel FETs)
OR
13
OP-90 PNP INPUT STAGE ALLOWSINPUT TO GO TO THE
NEGATIVE RAIL(SINGLE-SUPPLY INPUT)
VS
VBIAS
-VS
14
RAIL-RAIL INPUT STAGE
Bias compensation impossible Bias current changes
polarity with common-mode voltage CMRR is poor at
changeover Circuit is more complex(it is
actually two input stages)
VS
-VS
15
LOW VOLTAGE, HIGH SPEEDPRECISION ANALOG CIRCUITRY
Techniques to improve headroom affect circuit
performance The commonest is to make low-voltage
analog circuitry rail-rail The term rail-rail
can apply to input or output circuitry, or
both Rail-rail input stages have disadvantages
over classical types Rail-rail output stages have
disadvantages too, but minor ones
16
CLASSICAL OP AMP OUTPUT STAGE
Unity (X1) voltage gain Poor headroom
17
RAIL-TO-RAIL OUTPUT STAGESHave very small
headroom but high gain which may cause
stability problems
VS
VS
PMOS
PNP
OUTPUT
OUTPUT
NPN
NMOS
-VS
-VS
SWINGS TO RAILS LIMITEDBY SATURATION VOLTAGE
SWINGS TO RAILS LIMITEDBY FET ON RESISTANCE
(100W)
18
LOW VOLTAGE, HIGH SPEEDPRECISION ANALOG CIRCUITRY
A basic problem with modern low voltage analog
circuitsis that their supplies are generally
unipolar Classic precision analog circuits had
bipolar supplies (usually 15 V) Unsurprisingly
unipolar supplies complicate systems with bipolar
signals
19
LOW VOLTAGE, HIGH SPEEDPRECISION ANALOG CIRCUITRY
There are three simple ways of handling bipolar
signalsin a system with a unipolar power supply

• Generate a negative supply
• Provide an offset reference
• Use differential signals

20
LOW VOLTAGE, HIGH SPEEDPRECISION ANALOG CIRCUITRY
There are three simple ways of handling bipolar
signalsin a system with a unipolar power supply

• Generate a negative supply
• Provide an offset reference
• Use differential signals

Positive
Capacitors are 10 µF
supply
low-ESR types
ADM660
Negative
output
21
LOW VOLTAGE, HIGH SPEEDPRECISION ANALOG CIRCUITRY
There are three simple ways of handling bipolar
signalsin a system with a unipolar power supply

• Generate a negative supply
• Provide an offset reference
• Use differential signals

22
LOW VOLTAGE, HIGH SPEEDPRECISION ANALOG CIRCUITRY
There are three simple ways of handling bipolar
signalsin a system with a unipolar power supply

• Generate a negative supply
• Provide an offset reference
• Use differential signals

POSITIVE SUPPLY
ADC
AD8138
23
BASIC PROBLEMS OF HIGH-SPEEDPRECISION ANALOG
CIRCUITRY

• Most problems with the applications ofprecision
  high-speed analog circuitryarise from
  overlooking basic laws of physics

24
MURPHYS LAW
IN ANY SET OF CIRCUMSTANCES THE WORST THING THAT
CAN HAPPEN - WILL

• Any effect which you think can be disregarded,
  cant.
• Nature always sides with the hidden flaw.

25
IMPORTANT COROLLARIES TO MURPHYS LAW

• After it has worked successfully for two weeks,
  it will fail during the first public
  demonstration.
• Equipment blows to protect fuses.
• Interchangeable parts arent.
• Fail-safes dont.

26
BASIC LAWS INVOLVED IN THE DESIGNOF HIGH SPEED
MIXED SIGNAL CIRCUITRY

• Ohms Law
• Kirchoffs Law
• Faradays Laws
• Lenzs Law
• MURPHYS LAW!

27
PRINTED CIRCUIT BOARD TRACK RESISTANCE
OHMS LAW PREDICTS 1 LSB DROP IN 5cm OF STANDARD
PCB TRACK BUT WHO BELIEVES OHMS LAW?
FOR 1 OZ. COPPER r 1.724 X 10-6 WCM, Y
0.0038cm R 0.45 mW NUMBER OF
SQUARES R SHEET RESISTANCE FOR 1
SQUARE (Z - X), R 0.45mW/SQUARE
Z X
Z X
28
SKIN EFFECT
HF Current flows only
in thin surface layers
TOP
COPPER CONDUCTOR
BOTTOM
Skin Depth 6.61 f cm, f in Hz
-7
Skin Resistance 2.6 x 10 f ohms per
square, f in Hz
Since skin currents flow in both sides of a PC
track, the value of
skin resistance in PCBs must take account of this
29
SKIN EFFECT
MICROSTRIP
CONDUCTOR
(CURRENT FLOW NORMAL
TO DIAGRAM)
PC BOARD
HF CURRENT FLOWS IN ONE
(DIELECTRIC)
SIDE OF THE CONDUCTOR ONLY
GROUND PLANE
REGION OF RETURN
CURRENT FLOW
30
LEAKAGE RESISTANCE ON PC BOARDS
SURFACE LEAKAGE ON A PCB IS UNPREDICTABLE. R1 IS
NOT NECESSARILY LESS THAN R2.
IF A VULNERABLE CONDUCTOR IS SURROUNDED BY A
GUARD RING (ON BOTH SIDES OF THE BOARD) WHICH IS
AT THE SAME POTENTIAL AS THE CONDUCTOR IT IS
GUARDING, THE EFFECT OF LEAKAGE RESISTANCE WILL
BE MINIMIZED.
LEAKAGE RESISTANCE BETWEEN SURFACE TRACKS ON A
PCB IS GENERALLY MUCH LARGER THAN BETWEEN PLATED
HOLES.
31
A VIRGIN TEFLON STANDOFF INSULATORHAS MUCH LOWER
LEAKAGE THAN APRINTED CIRCUIT BOARD TRACK
32
ELECTROSTATIC DISCHARGE (ESD)

• All ICs are vulnerable to ESD damage sub-micron
  circuits are especially so
• Internal ESD protection circuits may degrade
  performance This is a design tradeoff
• ESD damage may not be catastrophic, but may
  degrade performance
• Keep IC out of potential discharge pathsTouch
  conductive foam or the equipment chassisbefore
  removing or inserting an IC

33
THE EQUIVALENT CIRCUITOF A RESISTOR IS NOT
BUT


34
GAIN OF 100 STAGE

• Resistor mismatch due to mismatch of temperature
  coefficients, mismatch of temperature (possibly
  due to self-heating), or both, can cause errors.
• Ideally, all resistors whose matching can affect
  accuracy should be fabricated on a single
  substrate.

100W
9.9kW
OUTPUT
0 - 10V
-
INPUT
0 - 100mV

35
HIGH VALUE RESISTORS

• Likely to be Less Stable and
• Non-Linear with Voltage

36
RESISTOR JOHNSON NOISE

• All Resistors Have Noise Vn Ö(4kTBR)
• It is possible to reduce the noise of a resistor
  by reducing T, B, or R but it is NOT possible to
  reduce k because Boltzmann is dead.

T is Absolute Temperature B is Bandwidth in
Hertz R is the Resistance in Ohms k is
Boltzmanns Constant (1.38E-23 J/K)
37
RESISTOR CAPACITANCE

• All Resistors Have Capacitance
• There is capacitance between the terminals
  -there is also capacitance to nearby circuitry

38
CAPACITANCE
0.00885 E A
r
C pF
d
2
A
d
A plate area in mm
d plate separation in mm
E dielectric constant relative to air
r
Commonest type of PCB uses 1.5mm
glass-fiber epoxy material with E 4.7
r
Capacity of PC track over ground plane
2
is roughly 2.8pF/cm
39
CAPACITIVE COUPLING EQUIVALENT CIRCUIT
IN
C

VCOUPLED
Z1
VN
-
Z1 CIRCUIT IMPEDANCE Z2 1/jwC VCOUPLED VN
Z1
ö ø
æ ç è
Z1 Z2
40
CAPACITIVE SHIELDING
CAPACITIVE SHIELD INTERRUPTS THE COUPLING
ELECTRIC FIELD
EQUIVALENT CIRCUIT ILLUSTRATES HOW A CAPACITIVE
SHIELD CAUSES THE NOISE CURRENTS TO RETURN TO
THEIR SOURCE WITHOUT FLOWING THROUGH Z1
41
CAPACITIVE EFFECTS DUE TO METAL LIDS
METAL (KOVAR) LID
CERAMIC

• SIDEBRAZE CERAMIC D.I.L. PACKAGES SOMETIMES HAVE
  ISOLATED METAL LIDS.
• THESE ARE VULNERABLE TO CAPACITIVE INTERFERENCE
  AND SHOULD BE GROUNDED (IF POSSIBLE).

42
STRAY CAPACITY BETWEEN CHIP BONDWIRES

0.2pF
43
WITH A HIGH PERFORMANCE CONVERTER ON AHIGH SPEED
DATA BUS, IT IS NOT POSSIBLE TO SHIELDTHE ANALOG
PORT FROM THE DIGITAL NOISE
IC
ANALOG PORT
FAST
DATA
BUS
44
BUFFER LATCH IN A SEPARATE PACKAGEUSED AS A
FARADAY SHIELD
CONVERTER
LATCH/
BUFFER
FAST
ANALOG PORT
DATA
BUS

• A BUFFER/LATCH CAN ACT AS A FARADAY SHIELD
  BETWEEN A FAST DATA BUS AND A HIGH PERFORMANCE
  CONVERTER.
• IT ADDS COST, BOARD AREA, POWER CONSUMPTION,
  RELIABILITY REDUCTION, DESIGN COMPLEXITY, AND
  IMPROVED PERFORMANCE.

45
EQUIVALENT CIRCUITS OF A REAL CAPACITOR
IDEAL CAPACITOR
MOST GENERAL MODEL OF A REAL CAPACITOR
HIGH FREQUENCY MODEL
LEAKAGE CURRENT MODEL
DIELECTRIC ABSORPTION (D.A.) MODEL
HIGH CURRENT MODEL
46
HIGH FREQUENCY DECOUPLING(REQUIRED EVEN BY LF
ANALOG CIRCUITS)
SURFACE MOUNT CAPACITOR
IDEAL HF DECOUPLING HAS 1. LOW INDUCTANCE
CAPACITOR (MONOLITHIC CERAMIC) 2. MOUNTED VERY
CLOSE TO THE IC 3. WITH NO LEADS (SURFACE
MOUNT) OR VERY SHORT LEADS 4. AND SHORT, WIDE
PC TRACKS IT MAY BE SHUNTED WITH A TANTALUM BEAD
ELECTROLYTIC TO PROVIDE GOOD LF DECOUPLING AS WELL
47
CAPACITORS HAVING SIGNIFICANT DIELECTRICABSORPTIO
N ARE USELESS FOR SAMPLE-AND-HOLD APPLICATIONS
V
V
A
B
CAPACITOR VOLTAGE
V
C
O
C
A
B
SWITCH POSITION
TIME
DIELECTRIC ABSORPTION CAUSES A BRIEFLY DISCHARGED
CAPACITOR TO RECOVER A PERCENTAGE OF ITS PREVIOUS
CHARGE ON BEING OPEN CIRCUITED
48
INDUCTANCE
2R
L, R in mm
L
2L
)
(
m
WIRE INDUCTANCE 0.0002L ln - 0.75
H
R
EXAMPLE 1cm of 0.5mm o.d. wire has an
inductance of 7.26nH
(2R 0.5mm, L 1cm)
L
W
H
2L
WH
m
H
STRIP INDUCTANCE 0.0002L ln
0.2235 0.5
)
(
)
(
L
WH
EXAMPLE 1cm of 0.25 mm PC track has an
inductance of 9.59 nH
(H 0.038mm, W 0.25mm, L 1cm)
49
NONIDEAL AND IMPROVED SIGNAL ROUTING
NONIDEAL SIGNAL TRACE ROUTING
LOAD
LOAD
IMPROVED TRACE ROUTING
LOAD
LOAD
LOAD
LOAD
50
BASIC PRINCIPLES OF INDUCTIVE COUPLING
INTERFERENCE CIRCUIT
SIGNAL CIRCUIT
M MUTUAL INDUCTANCE B MAGNETIC REFLUX
DENSITY A AREA OF SIGNAL LOOP wN 2pfN
FREQUENCY OF NOISE SOURCE V INDUCED VOLTAGE
wNMIN wAB
51
PROPER SIGNAL ROUTING REDUCESMUTUAL INDUCTANCE
Z1
V1
V2
Z2
52
MUTUAL INDUCTANCE AND SIGNAL COUPLINGIN RIBBON
CABLE
FLAT RIBBON CABLE WITH SINGLE RETURN HAS LARGE
MUTUAL INDUCTANCE BETWEEN CIRCUITS
SEPARATE AND ALTERNATE SIGNAL AND RETURN LINES
FOR EACH CIRCUIT REDUCE MUTUAL INDUCTANCE
TWISTED PAIRS REDUCE MUTUAL INDUCTANCE STILL
FURTHER
53
MAGNETIC SHIELDING
Magnetic shielding is not as easily accomplished
as electrostatic shielding, but may be done at HF
with a simple conducting screen, and at LF and DC
with a screen of high permeability material such
as Mu-metal. PC Copper foil is effective as a
magnetic shield above 20 MHz
54
RESONANT CIRCUITS FORMED BYDECOUPLED POWER LINES
IC
IC
SMALL SERIES RESISTANCE
EQUIVALENT CIRCUIT
CLOSE TO THE IC REDUCES THE Q
OF DECOUPLED POWER
LINE - RESONANT AT
1
f
p
2
LC
55
SATURATION

• Inductors with solid cores (magnetic alloy or
  ferrite) will behave non-linearly if required to
  carry too much current
• This is unlikely to be a direct problem in
  precision circuitry but may affect power supply
  noise performance and thus affect precision
  circuitry indirectly.

56
STRAY CAPACITANCE MAKES ALL INDUCTORSINTO TUNED
CIRCUITS
L
RESONANT FREQUENCY
1
f
2
p
LC
STRAY C
57
Q OR QUALITY FACTOR

• The Q of an inductor or resonant circuit is a
  measure of the ratio of its reactance to its
  resistance.
• The resistance is the HF and NOT the DC value.
• The 3 dB bandwidth of a single tuned circuit is
  Fc/Q where Fc is the center frequency.

Q 2pf L/R
58
KIRCHOFFS LAW
I
ADC
SIGNAL SOURCE
GROUND RETURN CURRENT
I
AT ANY POINT IN A CIRCUIT THE ALGEBRAIC SUM OF
THE CURRENTS IS ZERO OR WHAT GOES OUT MUST COME
BACK WHICH LEADS TO THE CONCLUSION THAT ALL
VOLTAGES ARE DIFFERENTIAL (EVEN IF THEYRE
GROUNDED)
59
THE IDEAL GROUND
SIGNAL
ADC
SIGNAL SOURCE
INFINITE CONDUCTIVITY ZERO VOLTAGE
60
A MORE REALISTIC GROUND
SIGNAL
ADC
SIGNAL SOURCE
VOLTAGE DUE TO SIGNAL CURRENT AND (PERHAPS)
EXTERNAL CURRENT FLOWING IN GROUND IMPEDANCE
EXTERNAL CURRENT SOURCE
61
SUPPLY AND GROUND NOISE

• Digital circuitry is noisy
• Analog circuitry is quiet
• Circuit noise from digital circuitry carried by
  power and ground leads can corrupt precision
  analog circuitry
• It is advisable to separate the power and ground
  of the digital and analog parts of a system
• Analog and digital grounds must be joined at ONE
  point

62
ANALOG AND DIGITAL GROUND

• Monolithic and hybrid ADCs frequently have
  separate AGnd and Dgnd pins which must be joined
  together at the device.
• This is not done from a desire to be difficult,
  but because the voltage drop in the bondwires is
  too large to allow the connection to be made
  internally.
• The best solution to the grounding problem
  arising from this requirement is to connect both
  pins to system analog ground.
• It is likely that neither the digital noise so
  introduced in the system Agnd, nor the loss of
  digital noise immunity, will seriously affect the
  system performance.

63
Grounding ADCs DACs
Data Converters (ADCs and DACs)are accurate and
sensitive analog devices whoseanalog ports are
vulnerable to unwanted noise(most advice in this
lecture applies to both ADCs DACs) Mixed Signal
Systems(systems with both analog and digital
processing)often have separate analog and
digital ground planesin order to isolate their
sensitive analog signals fromthe noise which is
often present on the digital ground
64
Grounding ADCs DACs
ADCs DACsfrequently have separate analog and
digital ground pins(labelled, respectively, AGND
and DGND) These should be connected together
andto the analog ground plane of the system Even
if the data sheet suggests otherwise!
65
Grounding ADCs DACs
A PHILOSOPHICAL PROBLEM! AGND and DGND should
bothbe connected to the analogground plane of
the system The pin description DGND doesNOT
imply that this pin shouldgo to the system
digital ground
Systemanalogground
66
Grounding ADCs DACs
WHY NOT USE ONE PIN? At high current or high
frequency theimpedance of the converter
leadsprevents the use of a single ground pin Low
current/low frequency convertersoften do have
just one
67
Grounding ADCs DACs
SO WHY MUST THEY BEJOINED AT THE PACKAGE? Ground
noise at X can affect theanalog circuitry of the
convertervia stray capacitances This noise can
be minimisedby minimising the impedancebetween
DGND, AGND and thesystem analog ground
68
Grounding ADCs DACs
Analog ordigital supply
SUPPLY DECOUPLING The supply to the digital part
of theconverter must be decoupled to theDGND
pin with a low inductancecapacitor having
minimum possiblelead and PC track
impedance Digital VDD may be fed from thesystem
analog or digital supplies,but should be
isolated by a smallimpedance in either case
69
Grounding ADCs DACs
GROUND RETURN CURRENT The only current which
flowsbetween Analog and digitalsystem grounds
is the returncurrent of the digital interfaces
70
Grounding ADCs DACs
BEWARE OF THE BUS! NEVER connect a major data
busdirectly to an ADC or DAC It is a source of
noise and mostADCs cannot drive the load
71
Grounding ADCs DACs
BUFFER IT Put a buffer between adata bus and a
converter Even if the converter hasan internal
buffer It minimisesnoise feedthrough And may
improve ADCaccuracy by loweringpower dissipation
72
Grounding ADCs DACs
SLOW DOWN!(If you can) Fast logic edges at
aconverters digital portsare a source of
noise Slowing them down withRC networks
canreduce this noise But system timing maynot
allow it take care
73
Grounding ADCs DACs
SAMPLINGCLOCKS In order to minimise phasenoise
(jitter), which candevastate the performanceof
a sampled data system,the sampling clock
oscillatorshould be built on the systemanalog
ground
74
Grounding ADCs DACs
THIS GROUNDING SCHEMEIS ALMOST UNIVERSAL If a
converter contains nocomputation, or draws
lessthan 30mA supply currentit should use this
scheme If the data sheet suggestsotherwise the
data sheet isprobably incorrect Even the
MicroConverter should be grounded this way
Systemanalogground
75
Grounding ADCs DACs
BIG DSP DEVICESWITH CODECS AREAN
EXCEPTION These devices have high(gt100 mA)
transient currenton DGND and are
usuallydesigned to have goodnoise isolation
between DGND and the analogcircuitry they
should have DGND and AGND separately grounded
unless thedata sheet says otherwise
Systemanalogground
Systemdigitalground
76
Grounding ADCs DACs
If in doubt join AGND DGNDand connect them
tosystem analog ground
77
System AGND DGND
Sometimes it is not possible to
reducecommon-mode ground noise to a
levelcompatible with the noise immunity ofADCs
and the digital circuitry that they drive In the
past this problem was solved byoptical isolators
today there is a fastercheaper and
lower-powered solutionusing surface micromachine
technology
78
Introducing iCoupler Technology

• Magnetic RatherThan Optical Transmission
• High-Fidelity Galvanic Isolation
• Performance, Power, and Cost Improvements Over
  Optocouplers

ADuM1100 Digital Isolator
79
Magnetic-Based Isolation Technology
Driver Chip
Receiver Chip
Chip-to-Chip Bond Wires
Micromachined Low Loss Coil
Insulation Layer
IN
OUT
Receiver
Driver
Semiconductor Top Metal Coil

• Standard CMOS Driver and Receiver Circuits
• iCoupler Channels Integrated Easily With Other
  Semiconductor Circuits
• Optocoupler Mechanical and Electrical Limitations
  Eliminated

80
ADuM1100 Receiver Chip
-- Insulation --
MEMS Coil
CMOS Circuitry
Coil/Insulation Cross-Section
81
iCoupler Product Offerings to Provide Performance
and Integration Benefits
Integration Benefits Multi-Channel Multi-F
unction
OptocouplerSolution
µmIsolationSolution
µmIsolationSolution
OptocouplerSolution
ADC optos
Isolated ADC
82
GROUND PLANES

• One entire side or layer of a PCB is continuous
  grounded conductor.
• This gives minimum ground resistance and
  inductance but is not always sufficient to solve
  all grounding problems.
• Breaks in ground planes can improve or degrade
  circuit performance there is no general rule.
• Twenty years ago ground planes were difficult to
  fabricate. Today they are not.
• If your PCB facility objects to fabricating
  ground planes GET A NEW PCB FACILITY!

83
A SLIT IN THE GROUND PLANE CAN RECONFIGURE
CURRENT FLOW FOR BETTER ACCURACY
84
MICROSTRIP TRANSMISSION LINE
CONDUCTOR
w
377h
h
DIELECTRIC
Z ohms
o
w E
r
GROUND PLANE
85
BREAKS IN GROUND PLANE RAISE RESISTANCE
VIEW FROM
CONDUCTOR
SIDE OF PCB
BREAK IN GROUND PLANE
CROSSOVER ON
GROUND PLANE SIDE
SIGNAL
CURRENT A
RETURN CURRENT B
DIVERTS AROUND
RETURN CURRENT A
BREAK IN GROUND
DIVERTS AROUND BREAK
PLANE RAISING
IN GROUND PLANE
INDUCTANCE
RAISING INDUCTANCE
SIGNAL CURRENT B
RETURN CURRENTS A AND B MAY INTERACT
86
DIFFERENTIAL TRANSMISSIONMINIMIZES GROUND ERRORS
ONE CARD
ANOTHER CARD
RECEIVER
DIFFERENTIAL
WHERE
SIGNAL
TO
DIFFERENTIAL SIGNAL
YOU
YOU
WANT IT
WANT
HIGH C.M.R.R.
SINGLE-ENDED,
GROUND NOISE

• At DC and LF the receiver will be an
  instrumentation amplifier
• At HF the receiver will be a transformer
• There is no ideal receiver for video signals
  which have components from DC to HF

87
POWER SUPPLY NOISE

• Long-term variation (Long-term variations
  in voltage or AC line voltage)
• AC Line noise (Both 100/120 Hz
  ripple on rectifier output and transient noise on
  the AC line which passes to the DC output)
• Switching Noise (Digital noise from
  switching-mode power supplies)
• Power line noise transfer (Unwanted signals
  which pass from one part of a circuit to another
  via the common power supply)

88
SWITCHING-MODE POWER SUPPLIES

• Generate every imaginable type of noise and some
  inconceivable ones as well
• DO NOT USE THEM WHERE NOISE IS IMPORTANT
• If their use is unavoidable, do not relax and
  enjoy it, but take extreme precautions against
  all forms of noise
• Remember that a manufacturers design change in a
  bought-in switching mode power supply may alter
  its effects on your system noise without altering
  its published specification.
• When developing a system using a switching mode
  supply, it is instructive and often frightening
  to temporarily replace the switching supply with
  a battery or a linear supply and to remeasure the
  system noise!

89
ELECTROMAGNETIC NOISE GENERATION

• Circuits must be designed so that external E/M
  fields are minimized.
• This is done by shielding, decoupling, minimizing
  the area of HF current loops, and designing
  circuits which generate as little EMI as
  possible.
• ITS NOT JUST A GOOD IDEA
• ITS THE LAW!!

90
ELECTROMAGNETIC NOISE INTERFERENCE

• The world is full of radio transmitters.
• Police, taxis, broadcast, amateur, CB, cellular
  and cordless telephones, telemetry, and garage
  door openers.
• Do not imagine that your circuit will never
  encounter one!

91
EMI PREVENTION
PCB
SINGLE CERAMIC CAPACITOR
FERRITE
FERRITE BEAD AND CAPACITOR
BEAD
INTEGRATED PI-FILTER
INTEGRATED
PI-FILTER
WHERE HIGH E-M FIELDS ARE ENCOUNTERED,
CIRCUITRY SHOULD BE SCREENED BY A
GROUNDED CONDUCTING ENCLOSURE
92
Clock Noise in Sampled Data Systems
Sampled Data System
93
Clock Noise in Sampled Data Systems
Basic Sampled Data Systemconsists of an ADC and
a DSP Both require clocks, which may or may not
be synchronised to each other but using the
clock oscillator in the DSP to drive the ADC can
cause severe problems
94
Clock Noise in Sampled Data Systems
Clock timing errors (jitter) produce amplitude
errors
95
Clock Noise in Sampled Data Systems
SNR ENOB vs tjfor various input frequencies
96
Clock Noise in Sampled Data Systems
SOURCES OF JITTER Jitter in the converter and its
SHA The sampling clock generator itself The
signal route from the clock to the converter(s)
97
Clock Noise in Sampled Data Systems
SOURCES OF JITTER Jitter in the converter and its
SHA The sampling clock generator itself The
signal route from the clock to the
converter(s) Twenty years ago one of the most
important specifications of a sample and hold
circuit (SHA) was its jitter, today, although
jitter is still as important as ever, the
circuitry used in SHAs and converters has
improved so much that circuit jitter is rarely a
problem, although jitter due to power supply
noise can still occur when decoupling is
inadequate You should still check the data sheet
carefully for this specification!
98
Clock Noise in Sampled Data Systems
SOURCES OF JITTER Jitter in the converter and its
SHA The sampling clock generator itself The
signal route from the clock to the
converter(s) There are two types of clock
generator with poor phase noise- Oscillator
circuits which are intrinsically noisy Low-noise
oscillators which have been affected by
interference
99
Clock Noise in Sampled Data Systems
Relaxation Oscillators(such as the well-known
555) are vulnerable to noise, which causes their
threshold circuit to operate early or late and
thus causes jitter Do not use themas sampling
clocks
100
Clock Noise in Sampled Data Systems
Resonant (LC) orphase-shift (RC)circuitry
Phase-shift tuned-circuit oscillatorsare much
more stable, and the ones usingLC tuned circuits
have higher Q, and thereforeless phase noise,
than ones with RC networks But both sorts can be
used as sampling clocks
101
Clock Noise in Sampled Data Systems
A Crystal Oscillatoris a resonant oscillator
using a quartz crystal, which has a Q of many
thousand, as a resonator This results in better
phase noise They may be built with ICs but a
single bipolar transistor or FET may give better
performancethan an IC
102
Clock Noise in Sampled Data Systems
A Crystal Oscillatorbuilt with logic gates is
not nearly such a good oscillator as a
purpose-built one Especially if other gates on
the same chip are handling high-speed digital
signals which are not synchronous with the
oscillator cross-talk in such a case can cause
very bad phase noise
103
Clock Noise in Sampled Data Systems
Power Line Interference Any Crystal
Oscillatormust have its power supply adequately
decoupled lestpower line noise causesevere
phase modulation This is a very common causeof
poor oscillator performanceand great care is
needed toavoid it
104
Clock Noise in Sampled Data Systems
SOURCES OF JITTER Jitter in the converter and its
SHA The sampling clock generator itself The
signal route from the clock to the
converter(s) As the sampling clock goes from the
clock oscillatorto the ADC/SHA it can be
affected by two noise sources- Cross-talk from
other digital lines Common-mode noise between
analog and digital ground
105
Clock Noise in Sampled Data Systems
Crosstalk between lines Digital signal lines
couple capacitively and magnetically if they run
in parallel Because of logic noise immunity this
is not too serious for most digital signals
(unless the lines are too long) but it isa
problem for analog signals and for sampling
clocks A ground return path between each signal
line and the next minimisesthis effect at the
cost of an increasein board area A better
solution for a sampling clockis to run the line
well away from allother digital signals
106
Clock Noise in Sampled Data Systems
107
Clock Noise in Sampled Data Systems
Ground Noise The best way to eliminatejitter
caused by ground noise is to put the sampling
clock on the system analog ground
108
Clock Noise in Sampled Data Systems
Ground Noise Other ways to eliminatejitter
caused by ground noise include minimising
common-mode noise bythe use of a transformeror
a differential amplifier
109
Clock Noise in Sampled Data Systems
Noisy External Clock If a sampled data system
must be operated with an externally-provided
clock which has intolerable amounts of jitter it
is possible to remove the jitter by
reconstructing the clock signal with a carefully
designed PLL
110
HIGH SPEED LINEAR DESIGN SEMINAR

• EurIng James M. Bryant Head of European
  Applications
• ? (44) 7785-305598
• ? james.bryant_at_analog.com