MobileMAN%20%20Hardware%20development%20for%20the%20MAC%20module:%20current%20state%20and%20outlook%20%20by%20Ralph%20Bernasconi,%20Ivan%20Defilippis, - PowerPoint PPT Presentation

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MobileMAN%20%20Hardware%20development%20for%20the%20MAC%20module:%20current%20state%20and%20outlook%20%20by%20Ralph%20Bernasconi,%20Ivan%20Defilippis,

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MobileMAN Hardware development for the MAC module: current state and outlook by Ralph Bernasconi, Ivan Defilippis, Silvia Giordano, Alessandro Puiatti – PowerPoint PPT presentation

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Title: MobileMAN%20%20Hardware%20development%20for%20the%20MAC%20module:%20current%20state%20and%20outlook%20%20by%20Ralph%20Bernasconi,%20Ivan%20Defilippis,


1
MobileMAN Hardware development for the MAC
module current state and outlook byRalph
Bernasconi, Ivan Defilippis, Silvia Giordano,
Alessandro Puiatti SUPSI Manno Cambridge, March
23 2004
2
  • Contents
  • Introduction
  • Steps done
  • Where we are
  • Next steps
  • Data structure description
  • Cross-layering questions

3
  • IntroductionProjects SUPSI-DIE goals (reminder)
  • Provide flexible development- and test-bed for
    enhanced WLAN protocol (CNR)
  • Bursty responsive MAC
  • Better contention scheme (backoff) avoid
    collisions even for dense and active networks
  • Ensure compatibility with 802.11x
  • Provide few samples to partners
  • Provide inputs for new standard

4
Steps Done (1/5)
  • Analysis of the Market for the 802.11
    implementations
  • Which kind of solutions were present
  • Which solution best suited our needs
  • Cost
  • Reliability
  • Flexibility
  • Access to the software code
  • Access to the firmware
  • Easy development environment
  • Secure and prompt technical support

5
Steps Done (2/5)
  • Analysis of the implementation starting point in
    relation with the market analysis
  • Starting from scratch
  • Implementation fo all the chain MAC - BB - RF
  • Starting from a middle point
  • Implementation of the MAC only
  • Starting from an already implemented solution
  • Change software and firmware for our pourpose

6
Steps Done (3/5)
  • Choosed solution
  • Starting from a middle point
  • BB and RF already developed by Elektrobit AG
  • DT20 Modem
  • Ourselv MAC implementation on Texass Instrument
    DSP
  • TI C6713 board

7
Steps Done (4/5)
  • Analysis of 802.11 standard in deep
  • Procedures and flowchart for the TX/RX farther
    implementation
  • Implementations on a single board
  • CRC on FPGA
  • TX/RX between MAC and BB
  • Channel Sensig machanism on MAC, (MAC RF)
  • MAC TX mechanism on DSP
  • MAC RX mechanism on DSP
  • Standard Backoff mechanism
  • Regular 802.11 frame generation
  • Fragmented frame generation

8
Steps Done (5/5)
  • Duplicate above steps in a second board
  • Stress tests in TX between boards connected by
    cable
  • Stress tests in RX between boards connected by
    cable
  • Stress tests in TX/RX between boards connected by
    cable
  • Stress tests in TX/RX between boards in wireless
    mode

9
Where we are
  • TX/RX of regular 802.11 frames OK
  • Backoff mechanism implemented
  • TX/RX of fragmented frame OK
  • RTS/CTS/DATA/AK handshake not yet implemented

DT20 - Modems
Level-Switch interfaces
JTAG interface
TI C6713 boards
10
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11
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12
Next Steps
  • RTS/CTS/DATA/AK handshake
  • Test of Backoff standard
  • Implementation on a third board
  • Communication tests with three cards
  • Implementation of new Backoff algorithm
  • Communication between board and PC through
    FireWire interface
  • Implementation of Data structure

13
Data Structure description (1/4)
  • Memory slotted in parameterized slot length
    (default frame max length)
  • Descriptor mechanism for handling data
  • Different queues for managing data transfer
  • From MAC to PHY and from PHY to MAC
  • From MAC to Host and from Host to MAC
  • Implementation of priority mechanisms for each
    queue
  • Control flags in descriptor in which
  • DATA Frame
  • DATA parameters for/from cross-layering

14
Data Structure description (2/4)
Memory Data Area
Descriptor yn1
MAC header x
MAC h. yn1
Frame body x
Frame body yn1
FCS x
FCS yn1
Frame body x1
Descriptor xn
MAC to PHY Queue
MAC (DSP)
Frame body xn
Frame body xn1
Descriptor yn-1
Descriptor yn
MAC h. yn-1
Frame body yn-1
FCS yn-1
Frame
15
Data Structure description (3/4)
Memory Data Area
Frame body x
Frame body x1
Descriptor xn
MAC (DSP)
Begin
Frame body xn
Descriptor xn1
Descriptor y
MAC header y
Frame body xn1
Frame body y
Descriptor y1
Begin
FCS y
MAC h. y1
Descriptor y2
Frame body y1
FCS y1
Frame
16
Data Structure description (4/4)
Management of queues with different levels of
priority
17
Cross-Layering Questions
  • How we think to implement the cross-layering
  • A shared memory area in the host?
  • A s.m.a made in two blocks one in the host and
    one in the MAC?
  • Other?
  • Who is the manager of the cross-layering data
    flow?
  • In which way the layers access the cross-layer
    area?
  • Which parameters we have to put in the
    cross-layer area?

18
  • Questions?
  • Thanks for your attention!
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