AVR Microcontroller

1
AVR Microcontroller

• Embedded System Designing

Introduced by Eng. Abd-Elsalam
Boda_eng_at_hotmail.com
2
Course Outline

• Introduction.
• AVR microcontroller Architecture.
• C Review.
• Memories in AVR.
• I/O Ports.
• Interrupts, External Interrupts.
• Timers/Counters
• Timer/counter 0 8 bit timer/counter.
• Timer/counter 1 16 bit timer/counter.
• Timer/counter 2 8 bit timer/counter.
• Analog comparator AC.
• Analog to digital converter A/D.
• Serial peripheral interface SPI.
• USART.
• Two wire serial interface I2C.
• Applications According to the course flow.

3
Introduction

• Microprocessor vs. Microcontroller

ROM
RAM
Microcontroller
Micro- Processor
Serial Parallel Ports
I/O Port
Interrupt
Timer
4
Introduction

• Microprocessor
• Faster.
• General purpose.
• Expensive
• CPU is stand-alone, RAM, ROM, I/O, timer are
  separate.
• Designer can control the amount of ROM, RAM and
  I/O ports.
• It is cheaper compared to the microcontroller
  with the same features.

5
Introduction

• Microcontroller
• Slower.
• Stand alone operation.
• Cheaper.
• CPU, RAM, ROM, I/O and timer are all on a single
  chip(but fixed amount).
• for applications in which cost, power and space
  are critical.
• Single Operation.

6
Introduction

• Memory types
• There are several types of memory which is
  divided into RAM (Volatile ) and ROM and Flash
  memory (Non-Volatile) and each type is divided
  into sub types as follows
• RAM(Random Access Memory)
• SRAM(Static RAM)
• Very expensive
• Very high performance
• Constructed of Flip-Flops

7
Introduction

• RAM(Random Access Memory)
• DRAM(Dynamic RAM)
• Cheap
• Constructed from Capacitors so it needs to be
  refreshed periodically.
• It is divided into
• SDRAM(Synchronous DRAM)
• SDR-SDRAM(Single Data Rate)
• DDR-SDRAM(Double Data Rate)
• DDR-SDRAM has better performance and faster than
  the SDR-SDRAM and it is commonly used now in our
  computer

8
Introduction

• RAM(Random Access Memory)
• DRAM(Dynamic RAM)
• Cheap
• Constructed from Capacitors so it needs to be
  refreshed periodically.
• It is divided into
• SDRAM(Synchronous DRAM)
• SDR-SDRAM(Single Data Rate)
• DDR-SDRAM(Double Data Rate)
• DDR-SDRAM has better performance and faster than
  the SDR-SDRAM and it is commonly used now in our
  computer

9
Introduction

• ROM(Read Only Memory)
• ROM(ROM)
• PROM(Programmable ROM).
• EPROM (Erasable PROM).
• EEPROM(Electrically Erasable PROM).

10
Introduction

• Flash Memory
• It is non-volatile computer memory that can be
  electrically erased and reprogrammed. It is a
  technology that is primarily used in memory cards
  and USB flash drives for general storage and
  transfer of data between computers and other
  digital products. It is a specific type of EEPROM
  (Electrically Erasable Programmable Read-Only
  Memory) that is erased and programmed in large
  blocks

11
Introduction

• LEDS and Switches
• LED(Light Emitting Diode)
• A light-emitting diode (LED) is a semiconductor
  diode that emits light when an electrical current
  is applied in the forward direction of the
  device, as in the simple LED circuit.

12
Introduction

• Switches.
• Switches type
• Toggle switch.
• Pushbutton switch.
• DIP switch.

13
Introduction

• Switches
• The shown circuit is a sample switch active low
  circuit, when we press on the pushbutton the
  ATMEL pin will be connected to the ground,
  otherwise it will be connected to the VCC

14
Introduction

• Opto-isolators and Opto-couplers
• The Opto-coupler consists of the control part
  which is the photo-diode and the load part which
  is the photo-transistor.
• When the voltage is applied on the photo-diode,
  it emits light which turns the photo-transistor
  on (be in the saturation mode short circuit).
• It is very fast
• The Switch ON/OFF speed
• is up to120 MHz with high
• Performance Opto-Coupler.

15
Introduction

• Relays
• All Relays Operate Using the same principle.
• Consisted of a control circuit
• has a coil in the green color and a load
  circuit that has a switch in the red color.

16
Introduction

• Buffers
• Buffers are used to protect ICs from high
  current because it passes voltage and holds
  current
• Also data buffer is a region of memory used to
  temporarily hold data while it is being moved
  from one place to another.
• Buffers ICs like 74244, 74245.

17
AVR microcontroller Architecture.
18
AVR microcontroller Architecture.
19
ATmega16 Features

• From the data Sheet.

20
C Review

• Include Files according to Codevision
• AVR header files e.g. mega8535, mega16, 902313,
  tiny22,ect.
• C header files e.g. math.h, string.h, stdlib.h,
  stdio.h,...ect.
• Other useful header files e.g. Delay.h, lcd.h,
  spi.h, I2C.h, Gray.h,ect.

21
C Review

• C functions
• C main function must be endless.
• Other function could be used.
• Function prototype declaration.
• Return-type function-name(Arguments or the
  inputs)
• Function itself.
• Return-type function-name(Arguments or the
  inputs)

22
C Review

• Variable Declaration
• Type Size (Bits) Range
• bit 1 0 , 1
• char 8 -128 to 127
• unsigned char 8 0 to 255
• signed char 8 -128 to 127
• int 16 -32768 to 32767
• short int 16 -32768 to 32767
• unsigned int 16 0 to 65535
• signed int 16 -32768 to 32767

23
C Review

• Variable Declaration
• Type Size (Bits) Range
• long int 32 -2147483648 to 2147483647
• unsigned long int 32 0 to 4294967295
• signed long int 32 -2147483648 to 2147483647
• float 32 1.175e-38 to 3.402e38
• double 32 1.175e-38 to 3.402e38

24
C Review

• Variable Declaration
• Type Size (Bits) Range
• long int 32 -2147483648 to 2147483647
• unsigned long int 32 0 to 4294967295
• signed long int 32 -2147483648 to 2147483647
• float 32 1.175e-38 to 3.402e38
• double 32 1.175e-38 to 3.402e38

25
C Review

• Operators
• Assignment operator (xy) (, -, /, )
• Increment/decrement operator /--
• Equal operator ()
• Less than (lt) less than or equal (lt)
• Greater than (gt) less than or equal (gt)
• Not equal (!)
• Logical operators
• And () Bitwise AND ()
• Or () Bitwise OR()
• Not (!) Bitwise XOR()
• Complement ()
• Right shifted (gtgt) Left shifted (ltlt)

26
C Review

• If Statement
• If(condition is true)
• Do whatever here
• Else if (another condition is true)
• Do whatever here
• .
• Else
• Do a default operation

27
C Review

• The For statement
• For(initial condition increment)
• Do whatever here
• for (count 100 count gt 0 count--)
• for (count 0 count lt 1000 count 5)
• count 1
• for (x5 count lt 1000 count)
• for (count 0 count lt 100 )
• count
• for (i 0, j 999 i lt 1000 i, j--)
• bj ai

28
C Review

• While statement
• While(condition)
• Do whatever here
• Do
• while(condition)

29
C Review

• Arrays
• Char arr15
• Char arr2legend
• Char arr151,2,3,4,5
• Arr15 from arr10 to arr14
• Indexed by integer.
• Tow dimensional array x43
• Pointers
• Char x char xlegend
• x x
• Char x x x

30
ATmega16

• Pin description
• 4 ports A,B,C,D each has 8 pins.
• RESET input. A low level on this pin for longer
  than the minimum pulse length will generate a
  reset.
• XTAL1 Input to the inverting Oscillator amplifier
  and input to the internal clock operating
  circuit.
•  XTAL2 Output from the inverting Oscillator
  amplifier.
• AVCC is the supply voltage pin for Port A and the
  A/D Converter. It should be externally connected
  to VCC.
• AREF is the analog reference pin for the A/D
  Converter.

31
ATmega16

• Status Register
• Bit 7 I Global Interrupt Enable
• The Global Interrupt Enable bit must be set for
  the interrupts to be enabled. The individual
  interrupt enable control is then performed in
  separate control registers. The I-bit is cleared
  by hardware after an interrupt has occurred, and
  is set by the RETI instruction to enable
  subsequent interrupts. The I-bit can also be set
  and cleared by the application with the SEI and
  CLI instructions.
• asm(sei) asm(cli)

32
ATmega16

• Status Register
• Bit 6 T Bit Copy Storage
• Bit 5 H Half Carry Flag
• Bit 4 S Sign Bit, S N V
• Bit 3 V Twos Complement Overflow Flag
• Bit 2 N Negative Flag
• Bit 1 Z Zero Flag
• Bit 1 Z Zero Flag

33
ATmega16

• Stack Pointer
• The Stack is mainly used for storing temporary
  data, for storing local variables and for storing
  return addresses after interrupts and subroutine
  calls.
•  
• The AVR Stack Pointer is implemented as two 8-bit
  registers.

34
ATmega16 Memories

• In-System Reprogrammable Flash Program Memory
• The ATmega16 contains 16K bytes On-chip In-System
  Reprogrammable Flash memory for program storage.
• The Flash is organized as 8K x 16.
• The Flash memory has an endurance of at least
  10,000 write/erase cycles. The ATmega16 Program
  Counter (PC) is 13 bits wide.

35
ATmega16 Memories

• SRAM Data Memory
• 1120 Data Memory locations address the Register
  File, the I/O Memory, and the internal data SRAM.
  The first 96 locations address the Register File
  and I/O Memory, and the next 1024 locations
  address the internal data SRAM.

36
ATmega16 Memories

• EEPROM Data Memory
• The ATmega16 contains 512 bytes of data EEPROM
  memory. It is organized as a separate data space,
  in which single bytes can be read and written.
  The EEPROM has an endurance of at least 100,000
  write/erase cycles.
• EEPROM Read/Write Access
• There are a several registers we will deal with
• The EEPROM Address Register EEARH and EEARL.
• The EEPROM Data Register EEDR.
• The EEPROM Control Register EECR.

37
ATmega16 Memories

• The EEPROM Address Register EEARH and EEARL.
• EEPROM Data Register EEDR.

38
ATmega16 Memories

• The EEPROM Control Register EECR.
• Bit 3 EERIE EEPROM Ready Interrupt Enable
• Writing EERIE to one enables the EEPROM Ready
  Interrupt if the I-bit in SREG is set.
• Writing EERIE to zero disables the interrupt. The
  EEPROM Ready interrupt generates a constant
  interrupt when EEWE is cleared.

39
ATmega16 Memories

• The EEPROM Control Register EECR.
• Bit 2 EEMWE EEPROM Master Write Enable
• The EEMWE bit determines whether setting EEWE to
  one cause the EEPROM to be written. When EEMWE is
  set, setting EEWE within four clock cycles will
  write data to the EEPROM at the selected address
  If EEMWE is zero, setting EEWE will have no
  effect.
• When EEMWE has been written to one by software,
  hardware clears the bit to zero after four clock
  cycles. See the description of the EEWE bit for
  an EEPROM write procedure.

40
ATmega16 Memories

• The EEPROM Control Register EECR.
• Bit 1 EEWE EEPROM Write Enable.
• The EEPROM Write Enable Signal EEWE is the write
  strobe to the EEPROM. When address and data are
  correctly set up, the EEWE bit must be written to
  one to write the value into the EEPROM. The EEMWE
  bit must be written to one before a logical one
  is written to EEWE, otherwise no EEPROM write
  takes place.

41
ATmega16 Memories

• The following procedure should be followed when
  writing the EEPROM (the order of steps 3 and 4 is
  not essential)
• Wait until EEWE becomes zero.
• Wait until SPMEN in SPMCR becomes zero.
• Write new EEPROM address to EEAR (optional).
• Write new EEPROM data to EEDR (optional).
• Write a logical one to the EEMWE bit while
  writing a zero to EEWE in EECR.
• Within four clock cycles after setting EEMWE,
  write a logical one to EEWE.

42
ATmega16 Memories

• Cautions
• An interrupt between step 5 and step 6 will make
  the write cycle fail, since the EEPROM Master
  Write Enable will time-out.
• If an interrupt routine accessing the EEPROM is
  interrupting another EEPROM access, the EEAR or
  EEDR Register will be modified, causing the
  interrupted EEPROM access to fail. It is
  recommended to have the Global Interrupt Flag
  cleared during all the steps to avoid these
  problems.

43
ATmega16 Memories

• Cautions
• When the write access time has elapsed, the EEWE
  bit is cleared by hardware. The user software can
  poll this bit and wait for a zero before writing
  the next byte.
• When EEWE has been set the CPU is halted for two
  cycles before the next instruction is executed.

44
ATmega16 Memories

• The EEPROM Control Register EECR.
• Bit 0 EERE EEPROM Read Enable
• The EEPROM Read Enable Signal EERE is the read
  strobe to the EEPROM. When the correct address is
  set up in the EEAR Register, the EERE bit must be
  written to a logic one to trigger the EEPROM
  read. The EEPROM read access takes one
  instruction, and the requested data is available
  immediately.

45
ATmega16 Memories

• Cautions
• When the EEPROM is read, the CPU is halted for
  four cycles before the next instruction is
  executed.
• The user should poll the EEWE bit before starting
  the read operation.
• If a write operation is in progress, it is
  neither possible to read the EEPROM, nor to
  change the EEAR Register.

46
ATmega16 Memories

• void EEPROM_write(unsigned int uiAddress,
  unsigned char ucData)
• / Wait for completion of previous write /
• while(EECR (1ltltEEWE))
• / Set up Address and Data Registers /
• EEAR uiAddress
• EEDR ucData
• / Write logical one to EEMWE /
• EECR (1ltltEEMWE)
• / Start eeprom write by setting EEWE /
• EECR (1ltltEEWE)
•  

47
ATmega16 Memories

• unsigned char EEPROM_read(unsigned int uiAddress)
• / Wait for completion of previous write /
• while(EECR (1ltltEEWE))
• / Set up Address Register /
• EEAR uiAddress
• / Start eeprom read by writing EERE /
• EECR (1ltltEERE)
• / Return data from Data Register /
• return EEDR
•  

48
ATmega16 I/O Ports

• Three I/O memory address locations are allocated
  for each port, one each for the Data Register,
  Data Direction Register, and the Port Input Pins.
• The Port Input Pins I/O location is read only,
  while the Data Register and the Data Direction
  Register are read/write.
•  
• The DDxn bit in the DDRx Register selects the
  direction of this pin. If DDxn is written logic
  one, Pxn is configured as an output pin. If DDxn
  is written logic zero, Pxn is configured as an
  input pin.

49
ATmega16 I/O Ports

• If PORTxn is written a logic one when the pin is
  configured as an input pin, the pull-up resistor
  is activated. To switch the pull-up resistor off,
  PORTxn has to be written logic zero or the pin
  has to be configured as an output pin.
•  
• If PORTxn is written a logic one when the pin is
  configured as an output pin, the port pin is
  driven high. If PORTxn is written a logic zero
  when the pin is configured as an output pin, the
  port pin is driven low.
•  Reading the Pin Value Independent of the
  setting of Data Direction bit DDxn, the port pin
  can be read through the PINxn Register bit.

50
ATmega16 I/O Ports

• Register Description for I/O-Ports
• Port A Data Register PORTA
• Port A Data Direction Register - DDRA
• Port A Input Pins Address PINA

51
ATmega16 I/O Ports

• I/O ports registers are bit-addressable
  registers, in codevision you can use this
  feature
• If you want to get the second bit in the register
  DDRA you simply say DDRA.1 .
• If you intend to use IAR compiler - or any other
  compiler- you need first to declare the IO ports
  that youll use as bit-addressable register as
  following
• Method1
• Unsigned char porta _at_ port 0x3b
• SFR PORTA 0x3b
• define PORTA ((volatile unsigned char)0x3b)
• define bit(x) (1ltlt(x))
• DDRA bit(1) /set/
• DDRA bit(1)// clear
• DDRA bit(1) // complement.

52
ATmega16 I/O Ports

• Method1
• define bit(x) (1ltlt(x))
• define setbit(P,B) (P) bit(B) /set/
• define clrbit(P,B) (P) bit(B) //clear
• define cmpbit(P,B) (P) bit(B) // complement.
• Method2
• Typedef struct
• unsigned bit0 1,
• bit1 1,
• bit2 1,
• bit3 1, bit4 1, bit5
  1, bit6 1, bit7 1,
• IOREG
• define PORTA((IOREG )0x3B)
• Int iPORTA.bit1 PORTA.bit10

53
ATmega8535 Interrupts
54
ATmega16 Interrupts
55
ATmega16 Interrupts
56
ATmega16 Interrupts

• // Interrupt definitions for code vision
•  interrupt program address void
  my_function(void)
• // Place your code here
• // Interrupt definitions for IAR
• pragma vector program address __interrupt void
  my_function(void)
• // Place your code here

57
ATmega16 External interrupts

• The ATmega16 or ATmega8535 has three interrupt
  INT0,INT1 and INT2 each of them could be
  activated on the rising and/or falling edge or
  level sensed.
• To enable any interrupt of them the GICR is used.
• To select the mode of sensing the MCUCR MCUCSR
  is used.
• To sense the occurrence of the interrupt the CIFR
  is used.
• General Interrupt Control Register GICR

58
ATmega16 External interrupts

• MCU Control Register MCUCR

59
ATmega16 External interrupts

• MCU Control Register MCUCR

60
ATmega16 External interrupts

• MCU Control and Status Register MCUCSR
• Bit 6 ISC2 Interrupt Sense Control 2
• The asynchronous External Interrupt 2 is
  activated by the external pin INT2 if the SREG
  I-bit and the corresponding interrupt mask in
  GICR are set. If ISC2 is written to zero, a
  falling edge on INT2 activates the interrupt. If
  ISC2 is written to one, a rising edge on INT2
  activates the interrupt. Edges on INT2 are
  registered asynchronously. When changing the ISC2
  bit, an interrupt can occur. Therefore, it is
  recommended to first disable INT2 by clearing its
  Interrupt Enable bit in the GICR Register. Then,
  the ISC2 bit can be changed. Finally, the INT2
  Interrupt Flag should be cleared by writing a
  logical one to its Interrupt Flag bit (INTF2) in
  the GIFR Register before the interrupt is
  re-enabled.

61
ATmega16 External interrupts

• include ltmega8535.hgt
• // External Interrupt 0 service routine
• interrupt EXT_INT0 void ext_int0_isr(void)
• // Place your code here
• PORTC

• void main(void)
• PORTC0x00
• DDRC0xFF
• GICR0x40
• MCUCR0x02
• MCUCSR0x00
• GIFR0x40
• asm("sei")
• while (1)

62
8-bit Timer/Counter0 with PWM

• Timer/Counter0 is a general purpose, single
  channel, 8-bit Timer/Counter module.
• Timer/Counter Clock Sources
• The Timer/Counter can be clocked by an
  internal or an external clock source, The
  Timer/Counter is inactive when no clock source is
  selected When no clock source is selected the
  timer is stopped.
• The clock source is selected by the Clock Select
  logic which is controlled by the clock select
  (CS020) bits located in the Timer/Counter
  Control Register (TCCR0).
• Timer/Counter Interrupt Mask Register TIMSK
  to Enable the timer interrupts.
• Timer/Counter Interrupt Flag Register TIFR to
  monitor the timer interrupts
•  Timer/counter Register (TCNT0) hold the count
  value
• Output compare Register (OCR0) hold the value to
  be compared with the value in TCNT0.

63
8-bit Timer/Counter0 with PWM

• Timer/Counter Register (TCNT0)
• Output Compare Register (OCR0)

64
8-bit Timer/Counter0 with PWM

• Timer/Counter Control Register TCCR0

65
8-bit Timer/Counter0 with PWM

• Timer/Counter Control Register TCCR0
• Modes of Operation
• The mode of operation, i.e., the behavior of the
  Timer/Counter and the output compare pins, is
  defined by the combination of the Waveform
  Generation mode (WGM010) and Compare Output mode
  (COM010) bits.

66
8-bit Timer/Counter0 with PWM

• Timer/Counter Control Register TCCR0
• Modes of Operation
• Normal Mode In this mode the counting direction
  is always up (incrementing), and no counter clear
  is performed.
• The counter simply overruns when it passes its
  maximum 8-bit value and then restarts from the
  bottom (0x00). In normal operation the
  Timer/Counter Overflow Flag (TOV0) will be set in
  the same timer clock cycle as the TCNT0 becomes
  zero.
• The output compare unit can be used to generate
  interrupts at some given time. Using the output
  compare to generate waveforms in Normal mode is
  not recommended, since this will occupy too much
  of the CPU time.

67
8-bit Timer/Counter0 with PWM

• Timer/Counter Control Register TCCR0
• Modes of Operation
• CTC Mode Clear Timer On Compare In CTC mode
  the counter is cleared to zero when the counter
  value (TCNT0) matches the OCR0. The OCR0 defines
  the top value for the counter, hence also its
  resolution.
• This mode allows greater control of the Compare
  Match output frequency. It also simplifies the
  operation of counting external events. The
  counter value (TCNT0) increases until a Compare
  Match occurs between TCNT0 and OCR0, and then
  counter (TCNT0) is cleared.
• An interrupt can be generated each time the
  counter value reaches the TOP value by using the
  OCF0 Flag.

68
8-bit Timer/Counter0 with PWM

• Timer/Counter Control Register TCCR0
• Modes of Operation
• For generating a waveform output in CTC mode, the
  OC0 output can be set to toggle its logical level
  on each Compare Match by setting the Compare
  Output mode bits to toggle mode (COM010 1).
  The OC0 value will not be visible on the port pin
  unless the data direction for the pin is set to
  output.

69
8-bit Timer/Counter0 with PWM

• Timer/Counter Control Register TCCR0
• The waveform generated will have a maximum
  frequency of fOC0 fclk_I/O/2 when OCR0 is set
  to zero (0x00). The waveform frequency is defined
  by the following equation
• The N variable represents the prescale factor
  (1, 8, 64, 256, or 1024).
• As for the normal mode of operation, the TOV0
  Flag is set in the same timer clock cycle that
  the counter counts from MAX to 0x00.

70
8-bit Timer/Counter0 with PWM

• In CTC Mode

71
8-bit Timer/Counter0 with PWM

• In CTC Mode

72
8-bit Timer/Counter0 with PWM

• Timer/Counter Control Register TCCR0
• Modes of Operation
• Fast PWM Mode
• The fast Pulse Width Modulation or fast PWM mode
  (WGM010 3) provides a high frequency PWM
  waveform generation option.
• The fast PWM differs from the other PWM option by
  its single-slope operation (saw-tooth wave form).
  The counter counts from BOTTOM to MAX then
  restarts from BOTTOM. The generated wave form
  change from zero volt to five volt, then reset to
  zero.

73
8-bit Timer/Counter0 with PWM

• Timer/Counter Control Register TCCR0
• Modes of Operation
• Fast PWM Mode
• - In non-inverting Compare Output mode, the
  Output Compare (OC0) is cleared on the Compare
  Match between TCNT0 and OCR0, and set at BOTTOM.
• - In inverting Compare
• Output mode, the output
• is set on Compare Match
• and cleared at BOTTOM.

74
8-bit Timer/Counter0 with PWM

• In Fast PWM Mode
• the counter is incremented until the counter
  value matches the MAX value. The counter is then
  cleared at the following timer clock cycle.

75
8-bit Timer/Counter0 with PWM

• Timer/Counter Control Register TCCR0
• Modes of Operation
• Phase Correct PWM Mode
• The phase correct PWM mode (WGM010 1) provides
  a high resolution phase correct PWM waveform
  generation option. The phase correct PWM mode is
  based on a dual-slope operation (triangular wave
  form). The counter counts repeatedly from BOTTOM
  to MAX and then from MAX to BOTTOM.

76
8-bit Timer/Counter0 with PWM

• Timer/Counter Control Register TCCR0
• Modes of Operation
• Phase Correct PWM Mode
• In non-inverting Compare Output mode, the Output
  Compare (OC0) is cleared on the Compare Match
  between TCNT0 and OCR0 while up-counting, and set
  on the Compare Match while down-counting. In
  inverting Output Compare mode, the operation is
  inverted.

77
8-bit Timer/Counter0 with PWM

• Timer/Counter Control Register TCCR0
• Modes of Operation
• Phase Correct PWM Mode
• The dual-slope operation has lower maximum
  operation frequency than single slope operation.
  However, due to the symmetric feature of the
  dual-slope PWM modes, these modes are preferred
  for motor control applications. The PWM
  resolution for the phase correct PWM mode is
  fixed to eight bits.

78
8-bit Timer/Counter0 with PWM

• In phase correct PWM mode the counter is
  incremented until the counter value matches MAX.
  When the counter reaches MAX, it changes the
  count direction. The TCNT0 value will be equal to
  MAX for one timer clock cycle.

79
8-bit Timer/Counter0 with PWM

• Timer/Counter Control Register TCCR0
• Bit 7 FOC0 Force Output Compare
• The FOC0 bit is only active when the WGM00 bit
  specifies a non-PWM mode. However, for ensuring
  compatibility with future devices, this bit must
  be set to zero when TCCR0 is written when
  operating in PWM mode. When writing a logical one
  to the FOC0 bit, an immediate Compare Match is
  forced on the Waveform Generation unit. The OC0
  output is changed according to its COM010 bits
  setting. Note that the FOC0 bit is implemented as
  a strobe. Therefore it is the value present in
  the COM010 bits that determines the effect of
  the forced compare.
• A FOC0 strobe will not generate any interrupt,
  nor will it clear the timer in CTC mode using
  OCR0 as TOP.

80
8-bit Timer/Counter0 with PWM

• Timer/Counter Interrupt Mask Register TIMSK
• Bit 0 TOIE0 Timer/Counter0 Timer Overflow
  Interrupt Enable
• Bit 1 OCIE0 Timer/Counter0 Output Compare
  Match Interrupt Enable

81
8-bit Timer/Counter0 with PWM

• Timer/Counter Interrupt Flag Register TIFR
• Bit 0 TOV0 Timer/Counter0 Overflow Flag
• Bit 1 OCF0 Output Compare Flag 0

82
16-bit Timer/Counter1

• The 16-bit Timer/Counter unit allows accurate
  program execution timing (event management), wave
  generation, and signal timing measurement. The
  main features are
• True 16-bit Design (i.e., Allows 16-bit PWM)
• Two Independent Output Compare Units
• Double Buffered Output Compare Registers
• One Input Capture Unit
• Input Capture Noise Canceller
• Clear Timer on Compare Match (Auto Reload)
• Glitch-free, Phase Correct Pulse Width Modulator
  (PWM)
• Variable PWM Period
• Frequency Generator
• External Event Counter
• Four Independent Interrupt Sources (TOV1, OCF1A,
  OCF1B, and ICF1)

83
16-bit Timer/Counter1

• Timer/Counter Clock Sources
• The Timer/Counter can be clocked by an
  internal or an external clock source, The
  Timer/Counter is inactive when no clock source is
  selected When no clock source is selected the
  timer is stopped.
• The clock source is selected by the Clock Select
  logic which is controlled by the clock select
  (CS020) bits located in the Timer/Counter
  Control Register (TCCR1B).
• The Mode of operation is selected by (TCCR1A) and
  (TCCR1B).
• Timer/Counter Interrupt Mask Register TIMSK
  to Enable the timer interrupts.
• Timer/Counter Interrupt Flag Register TIFR to
  monitor the timer interrupts
•  Timer/counter Register (TCNT1)hold the count
  value
• Output compare Register (OCR1A/B) hold the value
  to be compared with the value in TCNT0.
• The input capture unit capture the timer value in
  the Input capture register (ICR1).
• Each of (TCNT1, OCR1A, OCR1B, ICR1) is a 16-bit
  register divided into high and low.

84
8-bit Timer/Counter1

• Timer/Counter1 TCNT1H and TCNT1L
• Output Compare Register 1 A (OCR1AH and OCR1AL)
• Output Compare Register 1 B (OCR1BH and OCR1BL)

85
8-bit Timer/Counter1

• Input Capture Register 1 (ICR1H and ICR1L)
• When ever edge change is occurred on
• the ICP1 the value of the timer which is in
• the TCNT1 will be copied in the ICR1.
• the Analog comparator output (ACO) in
• The Analog comparator control and status
• Register (ACSR) could be used in stead of the
• ICP to trigger the input capture unit.

86
8-bit Timer/Counter1

• Timer/Counter1 Control Register A TCCR1A
• Bits from 74 in Non PWM modes.

87
8-bit Timer/Counter1

• Timer/Counter1 Control Register A TCCR1A
• Bits from 74 in Fast PWM modes.

88
8-bit Timer/Counter1

• Timer/Counter1 Control Register A TCCR1A
• Bits from 74 in Phase correct PWM modes.

89
8-bit Timer/Counter1

• Timer/Counter1 Control Register A TCCR1A
• Bit 3 FOC1A Force Output Compare for Channel A
• Bit 2 FOC1B Force Output Compare for Channel B
• it is the value present in the COM1x10 bits that
  determine the effect of the forced compare.
• A FOC1A/FOC1B strobe will not generate any
  interrupt nor will it clear the timer in Clear
  Timer on Compare match (CTC) mode using OCR1A as
  TOP.
• FOC1A/FOC1B bits are always read as zero.

90
8-bit Timer/Counter1

• Timer/Counter1 Control Register B TCCR1B
• Wave Generation Mode Bits
• WGM1310

91
8-bit Timer/Counter1

• Wave Generation Mode Bits

92
8-bit Timer/Counter1

• Timer/Counter1 Control Register B TCCR1B
• Bits from 02 ? are the clock Select bits
• as in timer 0.
• Bit 7 ICNC1 Input Capture Noise Canceler
• Bit 6 ICES1 Input Capture Edge Select

93
8-bit Timer/Counter1

• Timer/Counter Interrupt Mask Register TIMSK(1)
• Timer/Counter Interrupt Flag Register TIFR

94
8-bit Timer/Counter1

• Modes of Operation
• Normal Mode
• The simplest mode of operation is the Normal mode
  (WGM130 0). In this mode the counting
  direction is always up (incrementing), and no
  counter clear is performed. The counter simply
  overruns when it passes its maximum 16-bit value
  (MAX 0xFFFF) and then restarts from the BOTTOM
  (0x0000). In normal operation the Timer/Counter
  Overflow Flag (TOV1) will be set in the same
  timer clock cycle as the TCNT1 becomes zero.
• The output compare units can be used to generate
  interrupts at some given time. Using the output
  compare to generate waveforms in Normal mode is
  not recommended, since this will occupy too much
  of the CPU time.

95
8-bit Timer/Counter1

• Modes of Operation
• Clear Timer on Compare
• In Clear Timer on Compare or CTC mode (WGM130
  4 or 12), the OCR1A or ICR1 Register are used to
  manipulate the counter resolution. In CTC mode
  the counter is cleared to zero when the counter
  value (TCNT1) matches either the OCR1A (WGM130
  4) or the ICR1 (WGM130 12). The OCR1A or ICR1
  define the top value for the counter, hence also
  its resolution. This mode allows greater control
  of the compare match output frequency. It also
  simplifies the operation of counting external
  events.

96
8-bit Timer/Counter1

• Modes of Operation
• Fast PWM Mode
• The fast Pulse Width Modulation or fast PWM mode
  (WGM130 5,6,7,14, or 15) provides a high
  frequency PWM waveform generation option. The
  fast PWM differs from the other PWM options by
  its single-slope operation. The counter counts
  from BOTTOM to TOP then restarts from BOTTOM.

97
8-bit Timer/Counter1

• Modes of Operation
• Phase Correct PWM Mode.
• The phase correct Pulse Width Modulation or phase
  correct PWM mode (WGM130 1,2,3,10, or 11)
  provides a high resolution phase correct PWM
  waveform generation option. The phase correct PWM
  mode is, like the phase and frequency correct PWM
  mode, based on a dual-slope operation. The
  counter counts repeatedly from BOTTOM (0x0000) to
  TOP and then from TOP to BOTTOM.
• The PWM resolution for the phase correct PWM mode
  can be fixed to 8-, 9-, or 10-bit, or
• defined by either ICR1 or OCR1A. The minimum
  resolution allowed is 2-bit (ICR1 or OCR1A set to
  0x0003), and the maximum resolution is 16-bit
  (ICR1 or OCR1A set to MAX).

98
8-bit Timer/Counter1

• Modes of Operation
• Phase Correct PWM Mode.