Combinational Logic

1
Chapter 4-part 2

• Combinational Logic

2
4-6 Decimal Adder
Add two BCD's
?
9 inputs two BCD's and one carry-in
?
5 outputs one BCD and one carry-out
?
Design approaches
?
A truth table with 29 entries
?
use uinary full Adders
?
the sum lt 9 9 1 19
?
binary to BCD
?
3
BCD Adder The truth Table
?
4
Modifications are needed if the sum gt 9
?
C 1
?
K 1
?
Z
Z
1
?
8 4
Z
1
Z
?
8 2
mo
x
ification
-
(10)
or 6
mo
d
ification
-
(10)
or 6
?
?
d
d
C K Z Z Z Z
8 4 8 2
5
Block diagram
?
6
Binary Multiplier
Partial products
?
AND operations
fig. 4.15
Two-bit by two-bit binary multiplier.
7
4-bit by 3-bit binary multiplier
?
Fig. 4.16
Four-bit by three-bit binary
multiplier.
Digital Circuits
8
4-9 Decoder
A n-to-m decoder
?
n
a binary code of n bits 2 distinct information
?
n
n input variables up to 2 output lines
?
only one output can be active (high) at any time
?
9
An implementation
?
Fig. 4.18
Three-to-eight-line decoder.
38
Digital Circuits
10
Combinational logic implementation
?
each output a minterm
?
use a decoder and an external OR gate to
?
implement any Boolean function of n input
variables
11
Demultiplexers
?
a decoder with an enable input
?
receive information
in a single line and transmits
?
n
it in one of 2 possible output lines
Fig. 4.19
Two-to-four-line decoder with enable input
12
Decoder Examples

• 3-to-8-Line Decoder example Binary-to-octal
  conversion.

D0 m0 A2A1A0 D1 m1 A2A1A0 etc
13
Expansion
?
two 3-to-8 decoder a 4-to-16 deocder
?
Fig. 4.20
4 ?16 decoder
constructed with two
3 x 8 decoders
a 5-to-32 decoder?
?
14
Decoder Expansion - Example 2

• Construct a 5-to-32-line decoder using four
  3-8-line decoders with enable inputs and a
  2-to-4-line decoder.

15
Combination Logic Implementation
each output a minterm
?
use a decoder and an external OR gate to
?
implement any Boolean function of n input
variables
A full-adder
?
S(x,y,z)S(1,2,4,7)
?
C(x,y,z)
S
(3,5,6,7)
C(x,y,z)
S
(3,5,6,7)
Fig. 4.21
Implementation of a full adder with 1 decoder
16
two possible approaches using decoder
?
OR(minterms of F) k inputs
?
n
NOR(minterms of F') 2 - k inputs
?
In general, it is not a practical implementation
?
17
4-10 Encoders
The inverse function of decoder
?
a decoder
z
D
D
D
D




1 3 5 7
The encoder can be implemented
y
D
D
D
D




2 3 6 7
with three OR gates.
x
D
D
D
D




4 5 6 7
18
An implementation
?
limitations
?
illegal input e.g. D
D
x1
?
3 6
The output 111 (¹3 and ¹6)
?
19
Priority Encoder
resolve the ambiguity of illegal inputs
?
only one of the input is encoded
?
D
has the highest priority
?
3
D
has the lowest priority
?
0
X don't-care conditions
?
V valid output indicator
?
20
The maps for simplifying outputs x and y
fig. 4.22
Maps for a priority encoder
21
Implementation of priority
x
D
D

Fig. 4.23
2 3
Four-input priority encoder
x

D
D D

3 1 2
V
D
D
D
D




0 1 2 3
22
4-11 Multiplexers
select binary information from one of many input
?
lines and direct it to a single output line
n
2 input lines, n selection lines and one output
line
?
e.g. 2-to-1-line multiplexer
?
Fig. 4.24
Two-to-one-line multiplexer
23
4-to-1-line multiplexer
?
Fig. 4.25
Four-to-one-line multiplexer
24
Note
n
n-to- 2 decoder
?
n
add the 2 input lines to each AND gate
?
OR(all AND gates)
?
an enable input (an option)
?
25
Fig. 4.26
Quadruple two-to-one-line multiplexer
26
Boolean function implementation
MUX a decoders an OR gate
?
n
2 -to-1 MUX can implement any Boolean function
?
of n input variable
a better solution implement any Boolean function
?
of n1 input variable
n of these variables the selection lines
?
the remaining variable the inputs
?
27
an example F(A,B,C) S(1,2,6,7)
?
Fig. 4.27
Implementing a Bolxean function with a multiplexer
28
procedure
?
assign an ordering sequence of the input variable
?
the rightmost variable (D) will be used for the
input
?
lines
assign the remaining n-1 variables to the
selection
?
Lines with construct the truth table
lines w.r.t. their corresponding sequ
?
consider a pair of consecutive minterms starting
?
from m
0
determine the input lines
?
29
Example F(A, B, C, D) S(1, 3, 4, 11, 12, 13,
14, 15)
Fig. 4.28
Implementing a four-input function with a
multiplexer
30
Three-state gates
A multiplexer can be constructed with three-state
?
gates
Output state 0, 1, and high-impedance (open ckts)
?
Fig. 4.29
Graphic symbol for a three-state buffer
31
Example Four-to-one-line multiplexer
Fig. 4.30
Multiplexer with three-state gates