Chapter 4 Combinational Logic

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• Chapter 4Combinational Logic

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Combinational Logic Circuit

• Combinational circuit logic circuit whose
  outputs at any time are determined directly and
  only from the present input combination.
• A combinational circuit performs a specific
  information-processing operation fully specified
  logically by a set of Boolean functions.
• Sequential circuit one that employ memory
  elements in addition to (combinational) logic
  gatestheir outputs are determined from the
  present input combination as well as the state of
  the memory cells.

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Introduction

• The state of the memory elements, in turn, is a
  function of the previous inputs (and the previous
  state).
• Its behavior therefore is specified by a time
  sequence of inputs and internal states.
• In many applications, the source and the
  destination are storage registers.
• A combinational circuit also can be described by
  m Boolean functions, one for each output
  variable.

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Block Diagram of a Combinational Circuit
Combinational Circuit
n inputs
m outputs
Fig. 4-1 Block Diagram of Combinational Circuit
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Analysis Procedure
ABC
(A B C)(AB AC BC) ABC
A B C
(A B C)(AB AC BC)
AB
(AB AC BC)
AB AC BC
AC
BC
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Design Procedure

• 1. Define the problem.
• 2. Determine the number of input/output
• variables.
• 3. Assign letter symbols to input/output
  variables.
• 4. Derive the that defines the required
• relationships between inputs outputs.
• 5. Obtain the simplified Boolean function for
  each
• output.
• 6. Draw the logic diagram.

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Code Conversion Example
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Maps for BCD to Excess-3 Code Converter
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Maps for BCD to Excess-3 Code Converter
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Code Conversion

• The expressions obtained may be manipulated
  algebraically for the purpose of using common
  gates for 2 or more outputs.
• w A BC BD A B(C D)
• x BC BD BCD B(C D) B(C D)
• y CD CD CD (C D)
• z D

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Logic Diagram for BCD to Excess-3 Code Converter
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Adder

• The most basic arithmetic operation is the
  addition of 2 bits. A combinational circuit that
• performs this operation is called a
  half-adder.
• A combinational circuit that performs the
  addition of 3 bits is called a full-adder, which
• can be implemented by 2 half-adders.

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Half Adder
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Full Adder
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Full Adder
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Implementation of FA
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Implementation of FA
S z ?(x ? y) z(xy xy) z (xy xy)
z(xy xy) z(xy xy) xyz
xyz xyz xyz The carry output is C z(xy
xy) xy xyz xyz xy
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Binary Adder

• Iterative Logic Array (ILA)

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Carry Propagation

• The total propagation time is equal to the
  propagation delay of a typical gate times the
  number of gate levels in the circuit.
• The longest propagation delay time in an adder is
  the time it takes the carry to propagate through
  the full adders.
• The number of gate levels for the carry
  propagation can be found from the circuit of the
  full adder.

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Carry Propagation
Ai
Si
Bi
Pi
Gi
Ci1
Ci

• pi carry propagate
• ci carry generate
• These two signals are common to all full adders
  and depend only on the input augend and addend
  bits.

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Carry Propagation

• Pi Ai ? Bi
• Gi AiBi
• The output sum and carry can be expressed as
• Si Pi ? Ci
• Ci1 Gi PiCi
• C0 input carry
• C1 G0 P0C0
• C2 G1 P1C1 G1 P1(G0 P0C0) G1
  P1G0 P1P0C0
• C3 G2 P2C2 G2 P2G1 P2P1G0
  P2P1P0C0

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Carry Lookahead Generator
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4-Bit Adder with Carry Lookahead
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Binary Subtractor

• Subtraction addition of minuend and
  2s-complemented subtrahend.
• Also can implement subtraction directlywith
  half-subtractors and full-subtractors.

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Subtractor
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4-Bit Adder Subtractor
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BCD Adder
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Binary Multiplier
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4-Bit by 3-Bit Binary Multiplier
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Magnitude Comparator
A A3A2A1A0 B B3B2B1B0 xi AiBi
AiBi (AB) x3x2x1x0
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Decoder
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2-to-4-Line Decoder with Enable Input
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4 ?16 Decoder Constructed with Two 3 ? 8 Decoders
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Combinational Logic Implementation
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Priority Encoder

• A priority encoder is an encoder that includes
  the priority function.

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Priority Encoder
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Multiplexers

• A multiplexer is a combinational circuit that
  selects binary information from one of many input
  lines and directs it to a single output line.

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A 4-to-1 Multiplexer
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Quadruple 2-to-1-Line Multiplexer
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Boolean Function Implementation
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Implementing a 4-Input Function with a Multiplexer
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Three-State Gates
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Multiplexers with Three-State Gates
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Three-State Gates
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2-to-1-Line Multiplexer
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Stimulus and Design Modules Interacion