GLAST Large Area Telescope:

1
GLAST Large Area Telescope Tracker
Subsystem WBS 4.1.4 5D ASIC Procurement
2
Overview

• LAT-PS-1279 General Overview of Tracker ASIC
  Procurement
• Design specifications LAT-SS-00169, LAT-SS-00170
  (released)
• Wafer procurement from MOSIS/Agilent
• LAT-PS-1201 (released) Front-end readout chip
  (GTFE)
• LAT-PS-1222 (released) Readout controller chip
  (GTRC)
• Fabrication completed this month (submitted
  December 2002)
• Wafer probing and ASIC screening at UCSC
• LAT-PS-1250 (release in progress)
• Wafer lapping, dicing, and inspection
• LAT-PS-1321 (draft spec in progress)
• Wafer lot acceptance testing (MIL-STD-883E,
  Method 5007.6)
• Radiation testing (See Presentation 2B)
• LAT-TD-1325 (draft)
• Destructive physical analysis
• Electronics qualification and acceptance testing

3
Wafer Procurement

• Vendor The MOSIS Service of the USC ISI.
• Checking of design files, including DRC on the
  layout
• Subcontracting for fabrication of the masks
  (Dupont)
• Subcontracting the wafer fabrication
• HP/Agilent 0.5 ?m, 3-metal, epitaxial process
  (AMOS14TB)
• Thorough electrical testing of process monitors
  on each wafer
• MOSIS guarantees that the wafers meet the Agilent
  process specifications
• MOSIS provides the test results in the form of
  e.g. physical transistor parameter, sheet
  resistance, etc.
• Extraction of Spice model parameters for each
  wafer lot
• BSIM3 V3.1 models for design verification,
  especially in case problems arise
• Shipment of wafers to SLAC
• LAT specifications LAT-PS-1201 and LAT-PS-1222
  (released)

4
Wafer Procurement Status

• The flight wafers are locked in a dry-nitrogen
  cabinet in the wafer-probing clean-room at UCSC.
• One wafer of each chip type was sacrificed to
  yield chips for testing.

5
ASIC Screening

• Procedures, QA provisions, and travelers
  LAT-PS-1250
• Detailed descriptions of the test vectors
• LAT-TD-247 for the GTFE
• LAT-TD-248 for the GTRC
• Carried out in a cleanroom at UCSC
• Conforms with the LAT contamination control plan
  (LAT-MD-404)
• Conforms with ESD controls in LAT-MD-228 and
  NASA-STD-8739.7
• Cascade automated probe station
• Custom probe cards interface to the VME readout
• Bad dice are automatically ink marked
• 100 testing of all functionality
• GTFE performance testing (to extent possible
  without SSDs)
• Data archived in an MS Access database

6
EM ASIC Screening

• Only limited wafer probing was achieved with the
  Engineering Model ASICs
• The GTRC probe card had fatal problems (such as
  the probes being put on backwards by the vendor)
  and did not work. A new card has since been
  built and is functional at the full clock rate.
• The GTFE probe card could only operate at 2 MHz,
  due to excessive capacitive loading on the IC
  output drivers. The chip-to-chip outputs could
  not be tested at all. The probe card design has
  been updated and new cards built to correct these
  problems. It now operates at 20 MHz and tests
  all functionality.
• The probe station operation was not integrated
  with the test program. We have since updated out
  software to enable fully automated processing of
  an entire wafer plus automatic marking of bad
  dice.
• Incomplete IC testing caused problems during the
  EM MCM assembly. The wafer test system is now
  much improved and is ready for flight production.

7
Flight ASIC Screening

• The Cascade automated probe station at the Santa
  Cruz Institute for Particle Physics.
• Located in a small clean room that is dedicated
  solely to wafer probing.
• In addition, it is under a downflow hood with
  extra HEPA filters.
• The work area has recently been upgraded to
  conform to LAT contamination control and ESD
  control requirements.
• Workers have been formally trained in ESD and
  cleanroom procedures.
• Wafers are stored in a locked dry-nitrogen
  cabinet in this room.

8
Flight ASIC Screening

• Status
• Final versions of both probe cards are in hand
  and tested.
• Software details are being finalized and tested
  and the software put under configuration control.
• The procedure (LAT-PS-1250) is in the
  review/release process.
• The clean room has been updated for procedures,
  ESD, etc. and was inspected.
• A date is set to train personnel in clean-room
  and ESD procedures.

New GTRC probe card under test in a manual probe
station.
9
Wafer Lapping Dicing

• Specification, LAT-PS-01321, in progress.
• A single vendor will do the following
• Lap the wafers from 610 microns to about 270
  microns. This improves the wire bonding on the
  MCM
• Dice the wafers to our specified die size
• Pick the dice, separate the chip types, and
  separate bad dice from good dice (according to
  ink markings) into waffle packs.
• Visually inspect the dice to reject
• Scratches or chipped edges
• Inked dice
• Dice of the wrong chip type
• Ship the completed waffle packs to Teledyne
• Perform wafer lot acceptance testing on each lot
  according to MIL-STD-883E, Method 5007.6

10
ASIC Qualification Acceptance

• Qualification and acceptance testing of the ICs
  cannot be done on the bare dice in any practical
  way.
• Therefore, the qualification and acceptance tests
  are those pertaining to the completed MCMs
  (Presentation 7C).
• Qualification
• 38 MCMs from the initial production, including 2
  for DPA.
• DPA of some bare dice.
• Acceptance all MCMs
• Complete functional tests of finished MCMs
• Noise, threshold, and gain performance (without
  the SSD load)
• Thermal cycles to acceptance levels
• Burn-in
• MCMs failing acceptance testing or not 100
  functional after burn-in (except for possibly
  ltlt1 bad individual amplifier channels) must be
  discarded.
• Radiation testing (Presentation 2B) ICs mounted
  on mini MCMs.