Chapter 9 High Speed Clock Management

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Chapter 9 High Speed Clock Management
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Agenda

• Inside the DCM
• Inside the DFS
• Jitter
• Inside the V5 PLL

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The Digital Clock Manager
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Delay Lock Loop Block Diagram
Key ideas All clocks look the same (more or
less) Future clocks resemble current clocks (ie,
they are interchangeable)
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Simplified DLL Diagram
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Simplified Clock Tree Driving Four CLBs
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Aligining FBCLK with CLKIN
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Compensating for Setup Delays with DLL
Basic idea We can set Td_C 0
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Feedback from End Cell to Center Cell
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Additional Skew Reduction
Place DLL output Centrally, minimize Extra delays
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Completing the Picture
Clock tree Geometry is Crucial. Delivering
clock Uniformly to large Area is the
main Idea. Can deliver to Hundreds of LUT Flip
flops with Virtually identical skew
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DLL Zoom In
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Z2 Delay Exposed
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Main Delay Trim Detail
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Configuration Lock Process
General idea Dont assert Locked To outside
world until Done is asserted from The
configuration State machine Looks like
instantaneous Locking as part powers up
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Clock Doubling
Capture a period Identify end points Identify
middle (50) Identify 25, 75 Reassemble pieces
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Board Deskewing
We seek the ideal Situation with A,B And C all
tracking. However, different Environments. Takes
two DCMs To lock B to A, and C to A, but can
Make outside track Inside the chip
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More on Board Deskewing
Foreward path delay
Note how Locked is used To enable/ Disable
the Right hand device
Synchronization trick delivers four clocks Worth
of reset to the DCM and stops
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System Synchronous Applications
The Classic, single clocked synchronous system.
Looks good, but doesnt account for clock
arriving skewed all over the place to the right
hand block(s)
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Source Synchronous Applications
More common these days. The clock is recreated
by the middle box and forwarded to the boxes on
the right. This is what DDR SDRAM does, making
whichever device is blasting data, also provide
the clock for that data to the receivers. You
may receive in one case, but transmit in another
case, so often both boxes can transmit data and
clocks. Depends on which one is Sourcing the
Data.
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Compare System and Source Synchronous Timing
Most Source Synchronous devices have DLL units
inside. Data centering can select appropriate
setup time by phase Shifting the clock.
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Duty Cycle Correction
DLLs have ability to correct duty cycle to 50.
This means data clocking with the rising edge has
same setup window as data clocking with the
falling edge.
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Digital Frequency Synthesizer Capabilities
Its nice to distribute slow, external clocks and
be able to increase speed within the device.
Frequency synthesis allows this.
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Basic Internal DFS Structure
Output Control manages Up/down signal Task
adjust variable ring oscillator so CLKFX
CLKIN M D
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Some Common DFS Applications
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Fixed Value Phase Shift
See XAPP 462 ISE software lets you place a phase
shift constant Into the programmable phase
shifter, to assign clock edges
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Dynamic Fine Phase Shift Control
Can also do it dynamically, on the fly. Status
feedback gives indicator of where you Are in the
phase shifting
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Dynamic Phase Shift Controls
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Spartan 3 DCM Restrictions
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Clock Jitter
Jitter comes from many sources clock crystal
drift
noise
VCC ripple
SSO ground
bounce
temperature drift, gain change
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Cycle to Cycle Jitter
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Peak to Peak Period Jitter Distribution
Period jitter captured with digital sampling
scope (typically)
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Period Jitter Spec. as Unit Interval
Another point of view consider the amount of
time allocated for a data Bit on a line. Call
it a Unit Interval. Identify the amount of peak
to peak Jitter as a percentage of that Unit
Interval. Jitter is a performance thief, you
must assume it subtracts out of your setup time
(usually). Leaves less time available to handle
data properly
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Peak to Peak Jitter Calculation
Adding more devices is done by squaring the
device jitter and adding under the radical.
Deviation gets divided by n as number increases
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Jitter for DCM Cascades
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Virtex 5 Clock Management Tile
V5 Clock tile doesnt Have PMCDs, it Has PLLs,
instead.
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V5 PLL High Level
PFD Phase Frequency Detector CP Charge
Pump LF Low Frequency Filter VCO Voltage
Controlled Oscillator D Divisor counter M
Multiplier counter
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V5 PLL More Detail
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PLL/DCM Cascades
(preferred)
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Conclusions

• Clocking resources simplify design
• DCMs cover standard user domains working with the
  global clock networks
• DFS adds in extra clock multiplication
• Phase shifting allows tweaking clocks to better
  center to data
• PMCDs are quick/cheap ways to make more clocks
  and track together
• Jitter can be identified, managed and predicted
• PLLs can extend the frequency range and reduce
  overall jitter
• Virtex 6 and Spartan 6 resemble Virtex 5 DCMs