Principles of Computer Architecture Miles Murdocca and Vincent Heuring Chapter 8: Input and Output

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Principles of Computer ArchitectureMiles
Murdocca and Vincent HeuringChapter 8 Input
and Output
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Chapter Contents

• 8.1 Simple Bus Architectures
• 8.2 Bridge-Based Bus Architectures
• 8.3 Communication Methodologies
• 8.4 Case Study Communication on the Intel
  Pentium Architecture
• 8.5 Mass Storage
• 8.6 Input Devices
• 8.7 Output Devices

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Simple Bus Architecture

• A simplified motherboard of a personal computer
  (top view)

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Simplified Illustration of a Bus
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100 MHz Bus Clock
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The Synchronous Bus

• Timing diagram for a synchronous memory read
  (adapted from Tanenbaum, 1999).

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The Asynchronous Bus

• Timing diagram for asynchronous memory read
  (adapted from Tanenbaum, 1999).

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Bus Arbitration

• (a)Simple centralized bus arbitration (b)
  centralized arbitration with priority levels
  (c) decentralized bus arbitration. (Adapted from
  Tanenbaum, 1999).

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Bridge Based Bus Arch-itecture

• Bridging with dual Pentium II Xeon processors
  on Slot 2.
• (Source http//www.intel.com.)

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Programmed I/O Flowchart for a Disk Transfer
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Interrupt Driven I/O Flowchart for a Disk Transfer
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DMA Transfer from Disk to Memory Bypasses the CPU
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DMA Flowchart for a Disk Transfer
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Intel Memory and I/O Address Spaces
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Standard Intel Pentium Read and Write Bus Cycles
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Intel Pentium Burst Read Bus Cycle
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Intel Pentium Hold-Hold Acknow-ledge Bus Cycle
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A Magnetic Disk with Three Platters
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Manchester Encoding

• (a) Straight amplitude (NRZ) encoding of ASCII
  F (b) Manchester encoding of ASCII F.

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Organization of a Disk Platter with a 12
Interleave Factor
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Master Control Block
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Magnetic Tape
A portion of a magnetic tape (adapted from
Hamacher, 1990).
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Magnetic Drum
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Spiral Format for Compact Disk
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ECMA-23 Keyboard Layout
Keyboard layout for the ECMA-23 Standard (2nd
ed.). Shift keys are frequently placed in the B
row.
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The Dvorak Keyboard Layout
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Bit Pad with Puck
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Mouse and Trackball
A three-button mouse (left) and a three-button
trackball (right).
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Lightpen
A user selects an object with a lightpen.
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Touchscreen
A user selects an object on a touchscreen.
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Joystick
A joystick with a selection button and a
rotatable rod
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Laser Printer
Schematic of a laser printer (adapted from
Tanenbaum, 1999).
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Cathode Ray Tube
A CRT with a single electron gun
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Display Controller
Display controller for a 640480 color monitor
(adapted from Hamacher et al., 1990).
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VHDL Specification
Interface specification for the majority
component -- Interface entity MAJORITY is
port (A_IN, B_IN, C_IN in BIT F_OUT
out BIT) end MAJORITY Behavioral model for
the majority component -- Body architecture
LOGIC_SPEC of MAJORITY is begin -- compute
the output using a Boolean expression F_OUT lt
(not A_IN and B_IN and C_IN) or (A_IN and
not B_IN and C_IN) or (A_IN and B_IN and not
C_IN) or (A_IN and B_IN and C_IN) after 4
ns end LOGIC_SPEC
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VHDL Specification (cont)
-- Package declaration, in library
WORK package LOGIC_GATES is component AND3
port (A, B, C in BIT X out BIT) end
component component OR4 port (A, B, C, D
in BIT X out BIT) end component compone
nt NOT1 port (A in BIT X out
BIT) end component -- Interface entity
MAJORITY is port (A_IN, B_IN, C_IN in
BIT F_OUT out BIT) end MAJORITY
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VHDL Specification (cont)
-- Body -- Uses components declared in package
LOGIC_GATES -- in the WORK library -- import all
the components in WORK.LOGIC_GATES use
WORK.LOGIC_GATES.all architecture LOGIC_SPEC of
MAJORITY is -- declare signals used internally in
MAJORITY signal A_BAR, B_BAR, C_BAR, I1, I2, I3,
I4 BIT begin -- connect the logic gates NOT_1
NOT1 port map (A_IN, A_BAR) NOT_2 NOT1 port
map (B_IN, B_BAR) NOT_3 NOT1 port map (C_IN,
C_BAR) AND_1 AND3 port map (A_BAR, B_IN, C_IN,
I1) AND_2 AND3 port map (A_IN, B_BAR, C_IN,
I2) AND_3 AND3 port map (A_IN, B_IN, C_BAR,
I3) AND_4 AND3 port map (A_IN, B_IN, C_IN,
I4) OR_1 OR3 port map (I1, I2, I3, I4,
F_OUT) end LOGIC_SPEC