Title: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Chapter 8: Input and Output
1Principles of Computer ArchitectureMiles
Murdocca and Vincent HeuringChapter 8 Input
and Output
2Chapter Contents
- 8.1 Simple Bus Architectures
- 8.2 Bridge-Based Bus Architectures
- 8.3 Communication Methodologies
- 8.4 Case Study Communication on the Intel
Pentium Architecture - 8.5 Mass Storage
- 8.6 Input Devices
- 8.7 Output Devices
3Simple Bus Architecture
- A simplified motherboard of a personal computer
(top view)
4Simplified Illustration of a Bus
5100 MHz Bus Clock
6The Synchronous Bus
- Timing diagram for a synchronous memory read
(adapted from Tanenbaum, 1999).
7The Asynchronous Bus
- Timing diagram for asynchronous memory read
(adapted from Tanenbaum, 1999).
8Bus Arbitration
- (a)Simple centralized bus arbitration (b)
centralized arbitration with priority levels
(c) decentralized bus arbitration. (Adapted from
Tanenbaum, 1999).
9Bridge Based Bus Arch-itecture
- Bridging with dual Pentium II Xeon processors
on Slot 2. - (Source http//www.intel.com.)
10Programmed I/O Flowchart for a Disk Transfer
11Interrupt Driven I/O Flowchart for a Disk Transfer
12DMA Transfer from Disk to Memory Bypasses the CPU
13DMA Flowchart for a Disk Transfer
14Intel Memory and I/O Address Spaces
15Standard Intel Pentium Read and Write Bus Cycles
16Intel Pentium Burst Read Bus Cycle
17Intel Pentium Hold-Hold Acknow-ledge Bus Cycle
18A Magnetic Disk with Three Platters
19Manchester Encoding
- (a) Straight amplitude (NRZ) encoding of ASCII
F (b) Manchester encoding of ASCII F.
20Organization of a Disk Platter with a 12
Interleave Factor
21Master Control Block
22Magnetic Tape
A portion of a magnetic tape (adapted from
Hamacher, 1990).
23Magnetic Drum
24Spiral Format for Compact Disk
25ECMA-23 Keyboard Layout
Keyboard layout for the ECMA-23 Standard (2nd
ed.). Shift keys are frequently placed in the B
row.
26The Dvorak Keyboard Layout
27Bit Pad with Puck
28Mouse and Trackball
A three-button mouse (left) and a three-button
trackball (right).
29Lightpen
A user selects an object with a lightpen.
30Touchscreen
A user selects an object on a touchscreen.
31Joystick
A joystick with a selection button and a
rotatable rod
32Laser Printer
Schematic of a laser printer (adapted from
Tanenbaum, 1999).
33Cathode Ray Tube
A CRT with a single electron gun
34Display Controller
Display controller for a 640480 color monitor
(adapted from Hamacher et al., 1990).
35VHDL Specification
Interface specification for the majority
component -- Interface entity MAJORITY is
port (A_IN, B_IN, C_IN in BIT F_OUT
out BIT) end MAJORITY Behavioral model for
the majority component -- Body architecture
LOGIC_SPEC of MAJORITY is begin -- compute
the output using a Boolean expression F_OUT lt
(not A_IN and B_IN and C_IN) or (A_IN and
not B_IN and C_IN) or (A_IN and B_IN and not
C_IN) or (A_IN and B_IN and C_IN) after 4
ns end LOGIC_SPEC
36VHDL Specification (cont)
-- Package declaration, in library
WORK package LOGIC_GATES is component AND3
port (A, B, C in BIT X out BIT) end
component component OR4 port (A, B, C, D
in BIT X out BIT) end component compone
nt NOT1 port (A in BIT X out
BIT) end component -- Interface entity
MAJORITY is port (A_IN, B_IN, C_IN in
BIT F_OUT out BIT) end MAJORITY
37VHDL Specification (cont)
-- Body -- Uses components declared in package
LOGIC_GATES -- in the WORK library -- import all
the components in WORK.LOGIC_GATES use
WORK.LOGIC_GATES.all architecture LOGIC_SPEC of
MAJORITY is -- declare signals used internally in
MAJORITY signal A_BAR, B_BAR, C_BAR, I1, I2, I3,
I4 BIT begin -- connect the logic gates NOT_1
NOT1 port map (A_IN, A_BAR) NOT_2 NOT1 port
map (B_IN, B_BAR) NOT_3 NOT1 port map (C_IN,
C_BAR) AND_1 AND3 port map (A_BAR, B_IN, C_IN,
I1) AND_2 AND3 port map (A_IN, B_BAR, C_IN,
I2) AND_3 AND3 port map (A_IN, B_IN, C_BAR,
I3) AND_4 AND3 port map (A_IN, B_IN, C_IN,
I4) OR_1 OR3 port map (I1, I2, I3, I4,
F_OUT) end LOGIC_SPEC