Built-In Self-Test of Programmable I/O Cells in Virtex-4 FPGAs

1
Built-In Self-Test of Programmable I/O Cells in
Virtex-4 FPGAs

• Bradley F. Dutton, Lee W. Lerner, and Charles E.
  Stroud
• Dept. of Electrical Computer Engineering
• Auburn University

2
Outline of Presentation

• Previous Work
• Overview of Virtex-4 I/O Tiles
• Virtex-4 I/O BIST architecture
• ILOGIC/OLOGIC (input/output logic)
• SERDES (serialization/deserialization)
• I/O Standards
• Capabilities and Limitations
• Conclusion

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Previous Work in I/O BIST

• I/O BIST for Atmel AT94K (NATW06)
• Proposed BIST architecture for 100 stuck-at
  fault
• Configure bi-directional Cell Under Test (CUT)
• 23 BIST configurations to test all modes of
  operation
• AT94K I/O Cells are simple compared to Virtex-4
• 2 Flip-Flops, 4 Multiplexors, 3 I/O standards

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Virtex-4 I/O Tiles

• Two I/O Cells form I/O Tile
• Dedicated shift routing for SERDES data width
  expansion
• Routing to support complementary differential I/O
  standards
• All I/O Cells are identical
• 10 Flip-Flops
• 32 Multiplexors
• 69 I/O Standards
• More complicated than Atmel

I/O Cell
Input Logic (ILOGIC)
BSCAN EXTEST Access
To/from Device Resources
Input/Output Buffer (I/O Buffer)
Output Logic (OLOGIC)
From Device Resources
Input Logic (ILOGIC)
To/From Device Resources
Input/Output Buffer (I/O Buffer)
Output Logic (OLOGIC)
From Device Resources
I/O Cell
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Virtex-4 I/O BIST Architecture

• DSPs configured as counters to address 18 Kbit
  Block RAMs
• Block RAMs store deterministic and pseudorandom
  test patterns
• Greater controllability of test patterns
• Multiple TPGs address alternating rows of BUTs
• Bidirectional I/O buffers under test (BUTs)

TPG
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Virtex-4 I/O BIST Architecture
DSP
DSP
BRAMs
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ILOGIC/OLOGIC Fault Coverage

• Can only test bi-directional buffer modes
• Two undetected faults result

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SERDES Overview
ISERDES
O
D
Q1
TO FPGA INTERNAL RESOURCES
Q2
ISERDES serial to parallel conversion
Q3
Q4
Q5
CLK
Q6
CLKDIV
BITSLIP
CE1
CE2
FROM FPGA INTERNAL RESOURCES
DLYCE
DLYINC
DLYRST
REV
TO OTHER ISERDES IN I/O TILE
SHIFTIN1
SHIFTOUT1
SHIFTIN2
SHIFTOUT2
SR
OCLK
OSERDES
T1
T2
T
PAD
T3
T4
D1
D2
D3
Q
OSERDES parallel to serial conversion
D4
FROM FPGA INTERNAL RESOURCES
D5
Input Buffer
Output Buffer
D6
CLK
I/O Buffer
CLKDIV
OCE
REV
TO OTHER OSERDES IN I/O TILE
SHIFTIN1
SHIFTOUT1
SHIFTIN2
SHIFTOUT2
SR
TCE
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SERDES BIST Configurations

• SERDES requires more TPG and ORA lines
• Solution Block RAMs configured as 512x36bit
• Reduces total test vector count to 512
• 7 outputs per ISERDES require 7 ORAs
• Data serialization/deserialization requires high
  speed clock
• Solution instantiate clock divide circuitry and
  use the divided clock for TPGs and ORAs
• Amount of clock division depends on the data
  width
• Deserialized data must be identically aligned on
  ISERDES parallel outputs
• Solution add a training pattern to vector set
  and a Bitslip synchronizer circuit

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SERDES BIST Configurations

• Bitslip operation reorders deserialized data on
  inputs
• Bitslip synchronizer circuit aligns deserialized
  data prior to BIST
• Synchronizer EN line enables/disables circuit

Clock Cycle Init 1 2 3 4 5 6 7 8 9
ISERDES Q2 1 1 1 1 1 1 0 0 0 0
X FF X 0 1 1 1 0 1 0 0 0
Y FF X 0 0 1 1 0 0 1 0 0
Z FF 1 0 0 0 1 0 0 0 1 0
BITSLIP 0 0 0 1 0 0 0 0 0 0
Synchronizer Enable from TPG
To ISERDES
ISERDES Q2
D
Q
D
Q
D
Q
Y
Z
X
TPG Bitslip
CLKDIV
CLR
CLR
CLR
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I/O Standards

• I/O Standards are tested with ILOGIC/OLOGIC
  architecture
• 69 I/O standards, 9 are not bidirectional
• Four classes of I/O standards
• Single ended with Vref require an external
  reference voltage supplied to one I/O buffer per
  16 I/O
• DCI requires two external reference resistors in
  each I/O bank (64 I/O)
• Complementary differential requires some
  modification of the template architecture

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BIST Configuration Summary
I/O BIST Architecture of BIST Configurations Total BIST Clock Cycles (constant) Total Download Size (Kbits) (varies w/ size)
ILOGIC/OLOGIC 8 8192 4,034
SERDES 8 19,124 10,384
I/O Standards 62 496 5,828
TOTAL 78 27,812 20,246
Configuration file size for SX35 using compressed configuration files and partial reconfiguration files Configuration file size for SX35 using compressed configuration files and partial reconfiguration files Configuration file size for SX35 using compressed configuration files and partial reconfiguration files Configuration file size for SX35 using compressed configuration files and partial reconfiguration files

• I/O Standards configurations
• Less than 30 of configuration bits
• Less than 2 of BIST clock cycles
• 78 configurations, but smaller than 6 full
  downloads
• Total test time 405 msec for SX35

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Virtex-4 I/O BIST Configuraiton Generation
Programs

• Three XDL template file generation programs
• V4iobist ILOGIC, OLOGIC, I/O buffer logic
  resources
• V4iobistios SERDES logic resources
• V4iobistd complementary differential I/O
  standards
• Three XDL modification programs
• V4iobmod - ILOGIC, OLOGIC, I/O buffer logic
  resources
• V4iobmodios SERDES logic resources
• V4iobrmod I/O standards

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BIST Configuration Generation Process

• XDL Xilinx Description Language
• Can generate configurations for every Virtex-4
  device in any package
• FX12 not currently supported due to only 1 column
  of BRAMs in Power PC rows

BIST Programs
FPGA Editor
XDL file
XDL.exe
NCD file
BitGen.exe
BIT file
download
verification on FPGA
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All I/O Buffers Under Test in Virtex-4 FX20 as
viewed in Xilinx FPGA Editor
BRAMs for TPGs
I/O tiles under test and corresponding ORAs
DSPs for TPGs
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Summary

• 3 architectures in 78 configurations to test I/O
  cells in every mode of operation
• ILOGIC/OLOGIC
• ISERDES/OSERDES
• I/O Standards
• Tests both bonded and unbonded I/O cells
• Can be used for manufacturing or system level
  testing
• Connecting devices should be tri-stated
• Allows for testing at system frequencies