Configuration of FPGAs Using (JTAG) Boundary Scan

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Configuration of FPGAs Using (JTAG) Boundary Scan

• Chen Shalom
• www.cs.huji.ac.il/chensha

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Agenda

• FPGAs - overview
• Using FPGA from HDL to chip
• FPGA configuration Using JTAG
• Summary

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FieldProgrammableGateArray
- overview

• What are FPGAs ?
• Who makes FPGAs ?
• FPGA vs. CPLD
• Internal logic

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What are FPGAs ?

• FPGAs are programmable digital logic chips
• Can be programmed to almost any digital function
• FPGA can be configured many times with different
  functions
• If we have bug in our design- we fix it in the
  RTL and configure the FPGA again
• FPGAs are much faster than a design board with
  discrete components
• FPGAs are volatile devices

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Who makes FPGAs ?

• Xilinx Virtex, VirtexII, VirtexII-pro
• Altera
• Lattice
• Actel
• Quicklogic

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FPGAs vs. CPLDs
FPGAs CPLDs
fine-grain coarse-grain
RAM based- need to be downloaded at each power up EEPROM based- active at power up
Slower Faster
Can hold very large designs Can contain small designs only
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Internal Logic

• Thousands of Basic logic cells
• Each logic cell consist
• Small lookup table
• Some basic gates
• D-flipflop
• Logic cells can be connected using interconnect
  resources (wires/muxes)

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Using FPGAFrom HDL to chip
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Using FPGA

• Write synthesizable RTL in HDL
• Create the netlist from a HDL code
• Place and route according to the module
• constrains creating a binary file
• Configure into the FPGA

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FPGA configuration Using JTAG

• What does it means ?
• The JTAG interface
• Virtex Boundry Scan Instructions
• Virtex Boundry Scan Registers
• The configuration sequence

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What does it means ?

• Configuring an FPGA means downloading a stream of
  0s and 1s into it through some special pins
• The FPGA has 2 states- configuration mode and
  user mode
• Once the FPGA is configured, it goes into user
  mode and becomes active
• A special PROM on board configures the FPGA
  automatically at power-up

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The JTAG interface

• Standard JTAG commands can be used to take
  control of each pin in the chain
• In addition to testing, BS offers a device to
  have its own set of user defined instructions
• The added instructions, such as configure and
  verify, have increased the popularity of BS
  devices
• BS FPGAs has the ability to be configured through
  the BS chain

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Virtex Boundry Scan Instructions
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Virtex Boundry Scan Registers

• The Virtex family is fully compliant with BS.1
• In addition it supports some optional registers

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The configuration sequence

• Power up FPGA in configuration mode
• Get INIT1
• Load CFG_IN instruction
• Load bitstream from the BSR
• Load JSTART instruction
• Start up sequence
• The FPGA is operational !!

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An example for binary code

• 0011 0000 0000 0001 0010 0000 0000 0001
• -gt Header Write to COR
• 0000 0000 1010 0000 0011 1111 1111 1111
• -gt COR data sets SHUTDOWN 0
• 0011 0000 0000 0000 1000 0000 0000 0001
• -gt Header Write to CMD
• 0000 0000 0000 0000 0000 0000 0000 0101
• -gt Header Start command
• 0011 0000 0000 0000 1000 0000 0000 0001
• -gt Write to CMD
• 0000 0000 0000 0000 0000 0000 0000 0111
• -gt RCRC command
• 0000 0000 0000 0000 0000 0000 0000 0000
• -gt flush pipe

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Xilinx Virtex FPGA
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A JTAG cable

• Connects between the PC to the FPGA board

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The Ximpact tool
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Summary
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Az ma haya lanu sham ??

• FPGA is a programmable chip
• The best friend of the HW designer
• Built with many basic cells
• JTAG is a great interface for FPGAs
  configuration- added instructions and regs
• The configuration sequence
• Future IEEE 1532
• Element

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BGU Pictures
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Board infrastructure
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The BGU device
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The warm-air machine
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