BIST for Logic and Memory Resources in Virtex-4 FPGAs

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BIST for Logic and Memory Resources in Virtex-4
FPGAs

• Sachin Dhingra, Daniel Milton, and Charles Stroud
• Electrical and Computer Engineering
• Auburn University

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Outline of Presentation

• Overview of Virtex-4
• Architecture
• Operational Features
• Built-In Self-Test
• Architecture
• BIST for PLBs
• BIST for LUT-RAMs
• BIST for Block RAMs
• Experimental Results
• Test Time
• Memory Storage Requirements
• Summary

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Xilinx Virtex-4 FPGAs

• Configuration memory 4.7M to 50.8M bits of RAM
• PLBs 1,536 to 22,272
• 4 LUTs/RAMs (4-input)
• 4 LUTs (4-input)
• 8 FF/latches
• Block RAMs 48 to 552 18K-bit dual-port RAMs
• Also operate as FIFOs
• DSP cores 32 to 512, each includes
• 18x18-bit multiplier
• 48-bit adder accumulator
• PowerPC processors 0 to 2
• Supports soft processor cores
• Can write read configuration memory

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BIST for FPGAs

• Basic idea reprogram FPGA to test itself
• No area overhead or performance penalties
• Applicable to all levels of testing
• Application independent testing
• A generic test approach for a generic component
• Good diagnostic resolution
• Cost
• Memory to store BIST configurations
• Goal minimize number of configurations
• Download time to execute BIST configurations
• Goal minimize downloads and/or download time

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BIST for PLBs

• Program PLBs as
• Test Pattern Generators (TPGs)
• Output Response Analyzers (ORAs)
• Logic blocks under test (BUTs)
• Two test sessions
• Row or column orientation
• Good for dynamic partial reconfiguration

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Virtex-4 Logic BIST

• TPGs constructed from DSPs
• Accumulates constant 0x691
• Produces pseudo-exhaustive patterns
• Two TPGs per 4 rows of CLBs
• Each TPG drives alternating columns of BUTs
• ORAs in alternate columns
• 2 test sessions needed
• BUTs
• Logic slices need 10 configs
• Memory slices need 12 configs
• Not counting LUT RAMs
• Includes 2 for testing Shift Registers
• All slices test concurrently

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Virtex-4 LUT RAM BIST

• TPGs constructed from
• DSPs used as counter
• Block RAM used as ROM
• Store March Y test patterns
• March DPR for dual-port
• Memory slice LUT RAMs
• 64x1 single-port
• 32x2 single-port
• 16x2 dual-port
• ORAs in logic slices
• Only 1 test session
• BIST structure
• Groups of 4 rows
• 2 TPGs per 4 rows
• Drive memory slices in those rows

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BIST for Block RAMs DSPs

• Circular Comparison ORA
• Implemented in PLBs
• 1 ORA/core output
• Maximizes diagnostic resolution
• Two TPGs
• Implemented in PLBs
• Algorithms are a function of the BUT

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March LR Test for RAMs

• Detects
• neighborhood pattern sensitivity faults
• intra-word coupling faults
• bridging faults
• Notation
• ? address downward
• ? address upward
• ? address either way
• w0 write 0
• r1 read 1
• Length of test 16N
• N number of address locations
• Word-oriented memory Background Data Sequences
  (BDS) to detect pattern sensitivity coupling
  faults
• BDS ?log2(K)?1, where K data width
• Length of test (167?log2(K)?)N

March Y ?(w0) ?(r0,w1,r1) ?(r1,w0,r0) ?(r0)
March LR w/o BDS ?(w0) ?(r0, w1) ?(r1,w0,r0,r0, w1) ?(r1,w0) ?(r0,w1,r1,r1,w0) ?(r0)
March LR with BDS ?(w00) ?(r00, w11) ?(r11,w00,r00,r00, w11) ?(r11,w00) ?(r00,w11,r11,r11,w00) ?(r00,w01,w10,r10) ?(r10,w01,r01) ?(r01)
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Virtex II Block RAM BIST
BIST config Test Algorithm BDS Address Locations (A) Data Width Clock Cycles TPG Slices ORA Slices
1 March LR No 16K 1 2x14xA 62 N?D?2
2 March LR No 8K 2 2x14xA 62 N?D?2
3 March LR No 4K 4 2x14xA 64 N?D?2
4 March LR No 2K 9 2x14xA 64 N?D?2
5 March LR No 1K 18 2x14xA 68 N?D?2
6 March LR Yes 512 36 58xA 174 N?D?2
7 March s2pf No 512 36 14xA 64 N?D?2
8 March d2pf No 512 36 9xA 113 N?D?2
N of block RAMs D of data bits Total
clock cycles 829,952
Includes testing programmable controls Active
level of reset, clock enable, write enable Active
edge of clock Includes testing programmable write
modes Write-first, Read-first, No-change
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Virtex-4 Block RAM BIST
BIST Configuration Test Algorithm Address Locations (A) Data Width (D) Clock Cycles
1 March LR w/ BDS 512 36 58A
2 MATS 8K 2 25A
3 MATS 16K 1 25A
4 March s2pf 512 36 14A
5 March d2pf 512 36 9A
6 FIFO 4K 4 6A
7 FIFO 2K 9 6A
8 FIFO 1K 18 6A
9 FIFO 512 36 6A
10 FIFO ECC 512 64 3A
Total clock cycles 334,848 . TPG slice count 608 ORA slice count 72N where N block RAMs Total clock cycles 334,848 . TPG slice count 608 ORA slice count 72N where N block RAMs Total clock cycles 334,848 . TPG slice count 608 ORA slice count 72N where N block RAMs Total clock cycles 334,848 . TPG slice count 608 ORA slice count 72N where N block RAMs Total clock cycles 334,848 . TPG slice count 608 ORA slice count 72N where N block RAMs
Configurations 1-5 in one BIST download Configurat
ions 6-10 in another download Generic TPG for
each download
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Virtex-4 Block RAM BIST

• FIFOs
• Test full and empty flags
• Test almost flags (full and empty) via dynamic
  partial reconfiguration during BIST configuration
• Significant reduction in number of downloads
• ECC RAM
• Problem detecting faults in FT circuit
• Solution initialize RAM with Hamming errors
• Detect faults in bit error detection/correction
  circuit status outputs during full read cycle
  of RAM BIST
• Detect faults in Hamming code generation circuit
  during full write then read cycle of RAM BIST

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Reducing Test Time

• Orient BIST architecture to configuration memory
• Keep routing constant between configurations
• Downloading BIST configurations
• Partial reconfiguration
• Frame Data Register
• Allows multiple frame writes with same data
• Reduces frames written for configurations
• Optimize ordering of BIST configurations
• Retrieving BIST results
• Partial configuration memory readback
• Dynamic partial reconfiguration
• Read BIST results after set of BIST
  configurations
• Slight loss of diagnostic resolution

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Reducing Test Time
Partial Mem RB
Partial Reconfig
Full Mem RB
Full Config
Download Technique
ORA Results Retrieval Technique
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Reducing Test Time contd
Partial Mem RB
Partial Reconfig
Full Mem RB
Full Config
Download Technique
ORA Results Retrieval Technique
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Summary

• Virtex-4s large size and specialized cores pose
  challenges for developing efficient tests
• BIST Techniques
• Partial Reconfiguration
• Regular Test Structures
• New architectural operational features of
  Virtex-4 improve the efficiency of BIST
• BIST Results
• Test time improvements
• Over 12X improvement in Virtex-4 compared to 5X
  for Virtex
• Memory storage reduction
• 5X improvement for Virtex-4, 3X for Virtex