Memory In Processor Super Computer On Chip (MIP SCOC)

1
Memory In Processor Super Computer On Chip (MIP
SCOC)
MAPLD 2005 Paper 195
Venkateswaran Nagarajan Arvind M Karthik C
Karthik G Vishwanath V Viswanath K
Director, WAran Research FoundaTion, Chennai,
India. Research Trainee, WAran Research
FoundaTion, listed in alphabetical order.
On-board Space Applications

• Homogeneity of the node (Matrix, Vector, Graph
  Scalar)
• ALFUs (Algorithm Level Functional Units)
• Algorithm Level Instruction Set Architecture
  (ALISA)
• Compiler on Silicon (PCOS SCOS)

• Space Maneuvering
• Space Docking
• Space Medicine
• Remote sensing
• Satellite Imaging

Reconfiguration in MIP SCOC

• Identifying the Basic blocks
• Basic blocks based Reconfigurable Tree
• Implementing Inter and Intra reconfigurable ALFUs
• Reliability Massively Redundant ALFUs
• Timing Issues
• Dynamic Reconfiguration
• Block Level
• Intra Block

Low Power Aspects

• Simulation
• Synthetic application design
• Different class of algorithms
• Computation and Communication complexity
• Machine Instruction generation
• ALU instructions (Disassembler)
• MIP instructions (MIP compiler)

MIP IA-64
Decompiled No. of instructions of the Syn-app 30 10160
Memory Access Localized Not Localized
Instruction Set Simple Relatively Complex
Functional Units Atomic HLFUs Elementary units
Addressing Modes Least Addressing in the instructions Fixed
Conclusion

• Important Features
• Re-configurability
• Low Power
• Reliability
• Simulation Results