EECE 631 Microcomputer System Design Lecture 18: Timing

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EECE 631Microcomputer System DesignLecture 18
Timing

• Spring 2008
• Chris Lewis
• clewis_at_ksu.edu

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General System Block Diagram
CLKOUT
Transfer Acknowledge generation
Memory
TA
Delayed Chip Select
Chip Select Buffer
Chip Select
Chip Select Logic
Read/ Write Buffer
Micro
Delayed Read/Write line
Read/Write line
Delayed Addr lines
Address lines
Addr. Buffer
Delayed in one direction
Data Bus
Data Buffer
Data Bus
R
R
W
W
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System Block Diagram
Delayed Chip Select
Chip Select Buffer
Peripheral
Chip Select
Chip Select Logic -------- Micro
Read/ Write Buffer
Delayed Read/Write line
Read/Write line
Delayed Addr lines
Addr. Buffer
Address lines
Data Buffer
Data Bus
Data Bus
R
W
W
R
Delayed in one direction
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Simple Timing Problem

• Lets take a very simple problem. Adding a
  KM6256CL RAM with no buffers using the EBI chip
  selects. First look at memory.
• What do pins do?
• What to connect to?

KM62256CL 32K x 8 bit STATIC RAM
/CS
/WE
/OE
A0-A14
I/O0-I/O7
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The external memory ControllerAT91SAM7SE
(external memory)SDRAM interface
Clock Clock Enable Chip Select Bank Select Row
Signal Column Signal Write enable Data mask
enable Address Data
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Static Memory Controller
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Timing Analysis Procedure

• Develop the block diagram of the desired system.
• Determine whether using internal chip selects or
  external chip select as well as internal or
  external transfer acknowledge.
• Determine if buffers are needed.
• Collect timing data on the microprocessor/microcon
  troller, buffers, and all peripheral chips
  (memory, I/O, display driver, etc.)
• Determine where all pins on the peripheral device
  are connected.

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Placement in memory

• We must determine where to place it in memory so
  as not to conflict with existing onboard
  peripherals.
• Must get memory map.

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Placement in Memory

• EBI has special features for different types of
  memory
• Address buss has only 23 bits A0-A22
• Data buss has 32 bits
• 8 different chip selects
• Other control pins

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Mapping Memory (SMC)
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SMC Determines Range of Memory Locations available

• Unanswered Questions
• What happens when a
• single byte is read?
• What happens when an
• integer is read?
• How does the SMC/EBI/MC
• know what its getting from
• physical memory?

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Configuration

• Configure EBI and MC to use SMC for the address
  selected (typical montage of control registers)
• Configure to meet timing requirements if
  possible.
• Wait states
• External Wait Request
• Hold times
• Timing Analysis is Required

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Write Cycle Timing
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Read Cycle
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Configurable Timing
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Wait States
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Wait State
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1. Address and Chip select can be as short at one
clock cycle 2. Write-Enable is ½ clock cycle 3.
Data seems to follow this second half cycle, and
last for about a full clock cycle
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Each Wait state adds one full cycle to Address
and CS Each Wait state adds one half cycle to
Data and WE
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Where Are We?

• We are beginning to understand what each signal
  does, and who controls it.
• CS
• Address
• Data
• WE
• RD
• CLK
• Must READ the DESCRIPTIONS of various Timing
  Diagrams in the Manual
• Must understand how to configure the External
  Memory Controller
• Must decide which if any wait states are necessary

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Lets attempt, to only use standard Wait states
Why different?
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Timing Analysis

• Assemble timing diagrams and tables of
  specifications and requirements
• Memory
• CPU
• For each memory parameter
• Write an inequality equation that must be met
• Use the specifications given to make sure its
  met

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Graph the problem

• Draw the requirement or specification on the
  cpus timing diagram.
• Write an inequality
• Add up the terms to see if requirement is met.
• Pay careful attention to max/mins
• DO THIS FOR EACH TERM
• 9 terms for read cycle in our case
• 10 terms for write cycle in our case

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Timing Diagram for CPU
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The Memory
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Timing Diagrams for the Memory
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Parameter Table for Memory
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Timing Diagram for CPU
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Tables of Specs
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Timing Diagram for CPU
SMC_7 not labeled on diagram
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Consider Twc

• Does the address signal last long enough?
• Do we need wait states? How many?
• Memory stipulates the following requirements
• Twc_min 55,70ns
• Address must be valid at least 55 or 70 ns
• How long is address guaranteed to be valid by the
  cpu?
• 1/40Mhz 25ns
• Is 1 wait state enough for fast memory?
• Are 2 wait states enough for slow?

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Timing Analysis

• For each parameter, an equation must be written
  to ensure that the specification is met. These
  equations are inequalities.
• For memory to work it must allow sequences
  without contention on any line.
• Reading then reading
• Writing then writing
• Read then write
• Write then read

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Graph the problem

• Draw the requirement or specification on the
  cpus timing diagram.
• Write an inequality
• Add up the terms to see if requirement is met.
• Pay careful attention to max/mins
• DO THIS FOR EACH TERM
• 9 terms for read cycle in our case
• 10 terms for write cycle in our case

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Timing Diagrams for the Memory
Twc on both Read and Write
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Memory Requires Twc to be at least 5570ns
NOT HERE
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Address and Chip Select are same according to text
2.5ns accounts for rise and fall times relative
to cpmck My best guess is that rise and fall
times are 1.25 and 2.5ns MCK is 40 MHz, or 25ns,
therefore, we need Twc minimum allowed by memory
is 5570ns SMC_7 gt Twc (n1)t_cpmck -1.25 gt 5570
(inequality equation) N gt 2 for this to work
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Next Parameter Tcw
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Chip Select to end of write
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Add to CPU timing diagram
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Memory requires the time between chip select
going low till write goes high to be greater than
45(55) or 60(70) ns

• How long does the CPU guarantee that same time to
  be?
• SMC_18(provided as a min) relates these two
  signals, however, it measures from end of chip
  select, not the beginning
• SMC_7-SMC_18 gt Tcw

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Next Parameter Tas
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Address to WE
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Add to CPU timing diagram
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Problem

• (SMC_7 SMC_18 SMC_26)_min gt Tas
• SMC_7_min SMC_18_max-SMC_26_maxgtTas
• This would have been nice max vals not given
• Refer to previous description to determine
• WE occurs ½ clock cycle after address and CS
• 1/2MCK rise time gt Tas (0ns)

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Next Parameter Taw
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Taw mins(45,60 ns)
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Add to CPU timing diagram
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Problem

• min(SMC_7 SMC_18) gt Taw
• Min(SMC_7) Max(SMC_18) gt Taw
• This would have been nice max vals not given
• Refer to previous description to determine
• WE occurs ½ clock cycle after address and CS
• ½ Tclk t_rise Min(SMC_27) gt Taw

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Simple Timing Problem

• Consider adding a pair of KM6256CL RAM with no
  buffers using the Static Memory Controller (SMC)

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Timing Analysis

• For each parameter, an equation must be written
  to ensure that the specification is met. These
  equations are inequalities.
• For memory to work it must allow sequences
  without contention on any line.
• Reading then reading
• Writing then writing
• Read then write
• Write then read

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Static Memory Controller
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Consider Twc

• Does the address signal last long enough?
• Do we need wait states? How many?
• Memory stipulates the following requirements
• Twc_min 55,70ns
• Address must be valid at least 55 or 70 ns
• How long is address guaranteed to be valid by the
  cpu?
• 1/40Mhz 25ns
• Is 1 wait state enough for fast memory?
• Are 2 wait states enough for slow?

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Word Transfer?
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