Logic Built in Self Test

1
Logic Built in Self Test

• Neeraj Goel
• 2002vls017

2
Plan

• Introduction to Testing
• Various testing techniques
• BIST
• BIST and synthesis
• Various approaches and algorithm suggested
• Conclusion

3
Verification Vs Testing

• Verification
• Design errors
• Testing
• Manufacturing defects
• Aging defects
• In-field regular testing is required

4
Fault models and Detection

• Gate level Stuck-at Fault model
• Transistor level Stuck-at Fault model
• Bridging Fault Model
• Delay faults

5
Stuck at Fault model
A
Z
B
6
Bridging Fault Models
A
A
Resistive short
B
B
WAND
WOR
A
A
A
A
B
B
B
B
7
Fault models and Detection

• Gate level Stuck-at Fault model
• Transistor level Stuck-at Fault model
• Bridging Fault Model
• Delay faults

8
Testing Problem at Deep Sub-Micron

• Decreasing feature size
• Low power supply
• Increasing Number of pins
• Test equipment cost
• More test vectors
• Increasing gate count
• Memories, RF, MEMS on the chip
• Different test methodologies

9
Various DFT methods

• Full scan
• Boundary scan
• Logic BIST
• Quiescent current (IDDq test)

10
Scanning
FF3
FF1
FF4
ombinational LogicC
FF2
FF5
11
Scanning
FF3
FF1
FF4
Combinational Logic
FF2
FF5
12
Scan Design Techniques

• Flip-flop of design? Scan registers
• Use of Multiplexer
• Increased controllability and observability
• Two step synthesis approach scan mode and scan
  chain connection are done at second step
• Special scan registers

13
Full scan

• Additional wiring and mux area and performance
  effect
• Long test time
• Less effort in ATPG
• Cost increases with number of pins.

14
Full Scan (cont.)

• To prevent the problem other alternatives
• Multiple scan chains
• Partial scan design

15
Boundary Scan

• Use reduced number of pins
• Less cost of tester
• Need scannble latches at non-test I/O
• Additional cost of Mux (Performance)
• Large handling capabilities of ATPG system
  required

16
IDDQ test

• Relatively cheap
• Time require for each pattern is long
• Very convenient for bridge faults

17
Basic BIST Architecture
BIST Start
BIST Done
Test Controller
Pass/Fail
Output Response Analyzer (ORA)
Test Pattern Generator
System Outputs
Input Isolation circuitry
Circuit Under Test
System Inputs
18
Advantages of BIST

• Can be used at all level of testing
• System level testing in field
• At speed testing
• No need for external test machines
• Less I/O pins needed for testing
• Burn-in Test made easy
• No need for test vector development

19
Disadvantages of BIST

• Area overhead
• -more susceptibility to manufacturing
  defects
• Performance penalties
• Designing and verifying proper operation of BIST
  at design level.
• Additional risk in project

20
Traditional LBIST architecture- STUMPS

• Self-testing using MISR and parallel shift
  (Stumps)
• PRPG generate input for internal scan chains
• Compress the response in MISR
• Linear Feedback Shift Register (LFSR) generate
  pseudo random pattern.

21
Traditional LBIST architecture- STUMPS
22
Built-in Logic Block Observer
BILBO Flip-flop
Qi
Zi
B1
B2
23
Concurrent BILBO
R1-TGP
R1-TGP
Combinational Logic
Combinational Logic
R2-MISR
R2-TPG
R2-MISR
Concurrent BILBO Operation
BILBO Operation
24
LBIST Design flow4
LBIST controller, PRPG MISR, Phase
shifter, Compector
RTL description
RTL (co)simulation
RTL synthesis
Constraints
Gate level netlist
Gate level simulation
Scan insertion
Scan testable Gate level netlist
Test point insertion
Delay estimation
Static timing analysis
Test point generation
Layout
Delay Calculation
Test pattern generation
Static timing analysis
Backann. Re-simulation
25
BIST and Synthesis

• Circuit optimization for test
• Incomplete information available gt use
  estimation
• Goal
• Test concurrency
• Minimum area overhead

26
High level synthesis approach

• GOAL test concurrency
• Issues involved Hardware conflicts
• Probable Solution Choose the data path such that
  less conflicts

27
Synthesis stages

• Data-flow Scheduling for Testability
• Binding for Testability
• Test concurrency matrix
• Test Register Selection
• Incremental approach
• Test Path Definition
• Test point insertion
• Test Scheduling

28
SyncBIST Test Synthesis Overview
Behavioral Description
Behavioral Synthesis
Scheduling
binding
RTL Datapath
Structural Synthesis
Test register selection
Test Path Defination
Test Scheduling
Bist Data Path
BIST Test Plan
29
Some Experimental Results
Fault coverage comparison for Differential
Equation Circuit2
30
Another approach-by Gonzalez et al

• Minimizing testability cost and time by
• - multiple concurrent test sessions
• - register sharing

31
Algorithm1

• Preprocessing
• Built compatibility graphs of the FUs
• Built test status Matrix and call the cost
  function
• Apply minimal register allocation procedure

32
Yang and Muzios Approach3

• Module allocation and register allocation are
  performed incrementally
• -Module allocation is guided by testability
  balance technique
• -Register allocation aims at increasing the
  sharing degree

33
Algorithm

• Perform default allocation
• For all normal registers do
• Do life time analysis of variables
• end for
• For all register do
• Change to register according to functionality
• end for
• Repeat
• Perform module allocation
• Perform test register allocation
• for all normal register do
• Estimate the incremental hardware cost
• end for
• Select pair with smallest cost
• Merge the select pair and change the data
  path and registers accordingly.
• until no merger exist

34
Experimantal Results
ESTIMATED RESULTS ON Diffeq benchmark3
35
Moores Law for test Time vs Test Capital
36
Conclusion

• At deep submicron test cost and test time are
  major issues to be considers
• BIST can be a good option in this scenario
• To ensure good test performance, it is necessary
  to estimate the quality of test behavior during
  synthesis.

37
Reference

• J A Q Gonzalez, J R Amazonas, M Strum, W J Chau,
  Self Test Built-in plan for Data-Path Functional
  Units IEEE Latin American Test Workshop, 2000.
• A Orailoglu, G Harris, Microacritectural
  Synthesis for Rapid BIST Testing, IEEE trans. On
  CAD of ICS, June 1997
• L T Yang, J Muzio, Built in Self Testable Data
  Path Synthesis , In proc. Of IEEE Int. conf. On
  VLSI, April 2001.
• C Feige, M j Geuzebroek, Logic BIST technology
  evalution an industrial case study, European
  test workshop 2001.
• Charles E. Strode, A Designers guide to Built-in
  Self-test, Kluwer Academic Publisher,2002.