COMP541 Datapaths II - PowerPoint PPT Presentation

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COMP541 Datapaths II

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Let's take side trip into how these are done at low level. Then come back to look at detailed design of ALU. 6. Looking Inside. Cin also an input ... – PowerPoint PPT presentation

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Title: COMP541 Datapaths II


1
COMP541Datapaths II
  • Montek Singh
  • Mar 22, 2007

2
Topics
  • Continue datapath
  • Inside ALU
  • Addition and Subtraction
  • Implementing add/sub in ALU
  • Shifting

3
Datapath
  • Fairly complete datapath
  • Arithmetic
  • Logic
  • Shifter
  • One bit, R or L

4
ALU
  • This one has 2 control lines for arithmetic
  • S2 selects logical ops

5
Addition and Subtraction
  • Lets take side trip into how these are done at
    low level
  • Then come back to look at detailed design of ALU

6
Looking Inside
  • Cin also an input

7
Design of B Select Logic
  • Just straightforward truth table

8
4-Bit Circuit
  • Weve seen similar before

9
Now Add Logic Section
  • Mux to choose which

10
Logic Section Design
  • Generous number of operations

11
Resulting Control
12
Shifter First Thought
  • Make a parallel-load, bidirectional shift
    register
  • Anything wrong with that?

13
Takes Three Clocks
  • First clock loads shift reg
  • Second makes the shift
  • Third loads to destination reg
  • Any alternatives?

14
Mux as Shift Register
  • Combinational no clock

15
Is This Better?
  • Three short clocks may be faster than one limited
    by gate delays
  • But complex control
  • We have long ALU delay, so maybe this doesnt
    matter
  • Our one-clock shifter becomes multi instruction
    to shift n (gt1) bits

16
Shifting More Than 1 Bit
  • Barrel shifter

17
Impractical As-Is
  • When n gets larger, this becomes huge
  • Can use levels of muxes
  • Similar to carry-lookahead adder
  • Can design with transistors

18
Datapath
  • Higher-level view for hierarchical design
  • Can replace modules with same interface but
    different implementation

19
Register File
  • Can be fairly large (32 registers)
  • Memory with three addresses
  • D for write
  • A and B for read
  • What are
  • Inputs
  • Outputs

20
Function Unit
  • Arithmetic and shifter
  • Can be bypassed at output

21
Control Lines
  • Control inputs have been blended together into
    one control word (see next slide)

22
Operations of Func. Unit
23
Particular 8-bit Datapath
  • For examples to follow
  • Note that all control lines now have sizes and
    names
  • Look at each in next slide

24
Control Word
  • Collect all lines in a control word for
    convenience
  • Has 7 fields

25
Table of Fields (for reference)
26
Microoperation
  • Microoperation
  • Maps to

Field DA AA BA MB FS MD RW
Symb. R1 R2 R3 Reg Func Wr
Num. 001 002 003 0 00101 0 1
27
Other Examples
28
Using Numeric Notation
29
Have Simple Machine
  • With part of an instruction set
  • No branches, for example

30
Timing
  • Note that regs are latched on next clock

31
Next Time
  • Either look at control
  • or specifically at how to add memory to your MIPS
    design, and implement load and store
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