COMP541 Interrupts, DMA, Serial I/O

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COMP541Interrupts, DMA, Serial I/O

• Montek Singh
• April 24, 2007

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Interrupts

• Two main kinds
• Internal
• Error when executing an instruction
• Floating point exception
• Trying to access protected memory
• System call
• To request OS services
• External
• I/O

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Internal

• More complicated because may abort instruction
• Or OS could correct the situation
• Example Access to protected memory not allowed

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When Interrupt Occurs

• Interrupt enable register
• Sometimes levels of interrupts individually
  enabled/disabled
• PC is changed to new location
• One or more interrupt locations stored
• Or a fixed location
• Old PC saved to register or stack
• Many machines have stack pointer

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Registers

• Sometimes registers saved by hardware
• Some machines have one or more sets of registers
• On other architectures software must save
  registers
• Sometimes instruction to return from interrupt
• Otherwise, use the procedure return instruction,
  RET

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Cause of Interrupt

• Need way to determine what caused interrupt
• Note it can be more than one thing
• Vectored Interrupts
• Different types cause branches to different
  locations
• Sometimes prioritized
• Register to store cause

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Supervisory Mode

• Modern computers have user mode and one or more
  supervisory modes
• User mode restricted
• Cant write to many system registers, such as
  interrupt enable
• Cant write to some parts of memory
• Usually I/O restricted
• Interrupts cause switch to supervisory mode
• Question Which interrupts?

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Some Interrupt Hardware

• Interrupts ORed
• Response if IE and at end of instruction
• Ack interrupt
• Vector address to PC
• PC to stack

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Potential Microcode

• SP ? SP 1
• MSP ? PC
• SP ? SP 1
• MSP ? PSR
• PSR is processor status register
• EI ? 0
• INTACK ? 1
• PC ? IVAD

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Return Similar

• Very similar to return from procedure
• PSR holds IE bit
• Restoring PSR turns interrupts on

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Restarting Instruction?

• Imagine the interrupt (exception) was a page
  fault
• Need to get the page, and then rerun the
  instruction
• Easy instructions help out
• Otherwise may need to save some intermediate
  state
• Imagine block-move instruction

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Direct Memory Access (DMA)

• Programmed I/O is when CPU reads/writes every
  word
• Problem overhead is high nothing else getting
  done on CPU
• Especially for mass-storage devices like disk
• DMA Let device controller read/write directly
  to memory
• Challenges?

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Procedure

• DMA device takes over main bus
• Becomes bus master
• Asserts addresses
• Basically interfaces to memory or memory
  controller

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How?

• DMA device requests bus (assert BR)
• CPU grants request (assert BG)
• CPU takes its signals to Hi-Z

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Transfers

• Continuous DMA controller transfers all data
  (say a disk sector) at once
• As many memory cycles as data
• Burst DMA controller cycle steals, takes a
  cycle at end of every CPU instruction
• Note that now the chip that controls memory
  (northbridge), not CPU, is likely to do this

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End of DMA

• Controller needs to inform CPU
• De-assert BR
• Then CPU lowers BG and proceeds

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DMA Controller

• Needs typical I/O signals
• Interrupt request
• Status of device
• Also needs controls for DMA transfer
• Memory address
• Word count

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Block Diagram
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Typical Driver Interface

• Set the memory address
• Set word count
• Assert GO (usually bit in control word)
• DMA controller requests interrupt when transfer
  complete

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RS-232

• Asynchronous
• Both sides have precise clocks
• Agree on speed
• Receiver syncs during start bit

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USB

• One master
• The PC
• Idea was to have thin cables and plug and play

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USB Packet serial I/O

• Four wires total
• 5v and GND
• Two signal wires
• Twisted pair
• Differential signaling
• Differential 1 is D gt 2.8v and D- lt 0.3v
• Differential 0 is opposite
• Also a single-ended zero when D D- low (end of
  packet, reset, disconnect)

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Speed

• Three speeds
• High is 480 Mb/s
• Full is 12 Mb/s
• Low is 1.5 Mb/s
• Pull-up indicates full/low
• High speed starts as full, then handshakes and
  transitions
• High and low speeds interpret zeros and ones
  inverted.

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Coding

• NRZI
• Bit stuffing
• Since a string of 1s causes no transitions,
  synchronization may be lost
• A zero is stuffed in after six consecutive ones
• Sync field
• Each packet starts with a sync
• 8 bits 00000001

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Packets

• Wont go into details