ESE 570 Final Project

1
ESE 570 Final Project

• Due Wednesday, May 5, 2004, 430 pm

2
Choosing a Project

• Choose a group of three people
• Click HERE for list of project ideas.
• Choose one. Send me one email per group by
  Thursday, April 8th with
• Subject ESE570 Project Proposal
• Group members names
• Project Idea (if the project is not given as an
  example, also include a description so I know
  what you will build.
• Once your project is approved, begin work.
  Sending me your proposal earlier will mean you
  can get approved and can begin sooner.

3
Last Years Projects

• Hardware Implementation of DES Algorithm
• Finite State Machines
• N-bit Multiplier
• USB Device Controllers
• Memory
• USB Device Controller
• Viterbi Decoder

4
How to Get Started

• Find relevant reading materials.
• Develop a set of specifications that meet the
  requirements of the chosen application
• Make a high level rough sketch
• Divide and conquer
• Make a schedule and stick to it

5
Grading

• Research (15)
• Background and theory (5)
• System specifications / description (10)
• Design (40)
• Architecture to meet specifications (8)
• Design considerations (4)
• Brief description of individual blocks (8)
• Behavior (functional) level simulations (10)
• Transistor level descriptions and simulation with
  Hspice (10)

6
Grading Continued

• Layout (25)
• Layout and Design Rule Check (10)
• Extraction (5)
• Layout versus schematic (10)
• Performance Evaluation (20)
• Post layout simulation (15)
• Conclusion (5)

7
What to Submit

• Here is a suggested format for the final report
• 1. Background and Theory
• should include everything I need to know to
  understand the purpose of your chip
• 2. System Specifications
• Inputs/outputs, timing requirements,etc.
• 3. Architecture to meet specification
• Should include truth table/state diagram

8
What to Submit Continued

• 4. Design Considerations
• Sizing of transistors, timing issues, etc.
• 5. Block Descriptions
• A description of the operation of each block, and
  how it fits into the system hierarchy
• 6. Behavioral Simulations
• A functional (Verilog) simulation of the system
  as a whole, logic (Verilog or otherwise)
  verification of important blocks

9
What to Submit Continued

• 7. Transistor Level Schematics and Simulations
• Include the schematic of every block. Simulate
  every block, including the final chip. For
  groups of many similar blocks, it is okay to turn
  in a few representative simulations.
• Can choose Verilog or Hspice as appropriate.

10
What to Submit Continued

• 8. Layout
• Layout of all components at all levels, including
  final chip.
• 9. Extraction
• Extracted view of final chips and some
  representative components of your choosing
• 10. Layout Versus Schematic
• Do this for all components, but okay to only turn
  in LVS for entire chip (if full chip matches, I
  can infer that the components match.)

11
What to Submit Continued

• 11. Post Layout Verification with Hspice
• A layout simulation of the entire system with a
  variety of input conditions. This should
  demonstrate that the specifications have been
  met.
• Analysis of parameters (rise time, power
  consumption, etc.) at important nodes
• 12. Conclusion
• Difficulties encountered, changes that would be
  made if you were to do the project over, etc.

12
Some Design Tips

• Make everything modular, and test often at every
  step.
• Try to keep everything a standard rectangular
  shape, including final chip.
• Using Euler paths to create efficient layouts for
  complex gates is better than stringing together
  many simple gates

13
Some Design Tips Continued

• Always keep in mind big picture
• How am I going to route inputs / power to each
  block in the final layout?
• Use wide Vdd and Gnd lines, route these lines
  (and others, like clock) efficiently
• Dont route poly over a long distance

14
Some Final Tips

• Start early dont leave anything until last
  minute
• Periodically save backups
• Keep track of what needs to be turned in as you
  go along
• Check my Cadence page often for continued updates

15
Important Dates

• Thursday, April 8th
• Proposal Due by email to rciarcia_at_seas
• Wednesday, May 5th
• Project Due by 430 pm