IEEE Std. 1500 Introduction Reference paper : On Using IEEE P1500 SECT for Test Plug-n-Play

1
IEEE Std. 1500 IntroductionReference paper
On Using IEEE P1500 SECT for Test Plug-n-Play

• Erik Jan Marinissen, Rohit Kapur, Yervant Zorian
• Proceedings on International Test Conference,
  2000. Page(s)770 - 777
• Presenter Chi-Hung Lin

2
Abstract

• System chips are increasingly designed
  by embedding reusable cores. A core-based test
  strategy for such ICs is often attractive and
  sometimes even mandatory. IEEE P1500 SECT is a
  standard under development that standardizes a
  Core Test Language and a Core Wrapper, in order
  to facilitate plug-n-play core testing. In this
  paper, we describe how one standard supports both
  easy integration and interoperability as well as
  flexibility and scalability. Possible usage
  scenarios of the standard for core providers,
  core users, and EDA tool developers are sketched.

3
Whats the problem

• IP cores reuse design methodology
• Reuse of the cores test patterns
• Embedded cores testing vs. board level testing

4
Introduction

• IEEE P1500
• Focuses on standardizing at the interface between
  core provider and core user.
• Core test knowledge transfer
• Test access to embedded cores
• IEEE P1500 two main components
• Core test wrapper architecture (todays
  presentation)
• Core test language (CTL)

5
IEEE 1500 block diagram
6
IEEE 1500 scalable hardware architecture

• Wrapper Component
• Wrapper serial port (WSP)
• Wrapper parallel port (WPP)
• Wrapper instruction register (WIR)
• Wrapper bypass register (WBY)
• Wrapper boundary register (WBR)

• WSP
• WSI, WSO
• A set of WSC terminals
• The wrapper clock (WRCK)
• wrapper reset (WRSTN)
• SelectWIR
• CaptureWR
• ShiftWR
• UpdateWR
• WPP
• Parallel access mechanism for increased data
  bandwidth

7
Wrapper bypass register (WBY)

• WBY is connected between the WSI and WSO
  terminals of the WSP and can be shifted using
  protocol applied to the signals of the WSC
  terminals.

8
Wrapper boundary register (WBR)

• WBR operation modes
• Normal mode
• WBR does not interfere with the functional
  operation of the core.
• Inward facing (IF) mode
• Test mode where core inputs are controlled by the
  WBR and core outputs are observed by the WBR.
• Outward facing (OF) mode
• WFOs are controlled by the WBR and WFIs are
  observed by the WBR.
• Nonhazardous mode
• Core inputs are controlled to safe data by the
  WBR, and WFOs are controlled to safe data by the
  WBR.

9
Wrapper boundary register (WBR)

• WBR in serial interface

10
Wrapper boundary register (WBR)

• WBR in parallel interface

11
Wrapper instruction register (WIR)

• The WIR contains a shift stage, instruction
  decode, and update stage

12
WIR instructions

• WS_EXTEST instruction

13
WIR instructions

• WP_EXTEST instruction

14
WIR instructions

• WS_INTEST_RING instruction

15
WIR instructions

• WS_INTEST_SCAN instruction

16
IEEE 1500 core wrapper example
17
Relationship between IEEE 1500 and 1149.1
IEEE 1500 signals
IEEE 1149.1 signals
18
Glue Logic IEEE 1149.1 to 1500
19
WSP configurations for IEEE 1500 system chips

• Connecting multiple cores

Multiplexing
Daisy chain
Distribution
20
Core test language overview

• IEEE P1450.6 defines the CTL
• Using the CTL description of a core
• a wrapper can be constructed
• Test access mechanism (TAM) can be determined
• CTL is both human and computer readable
• CTL can be utilized for documentation purposes,
  as well as for driving chip test integration
  tools

21
CTL example
ScanStructures ScanChain wir_chain
ScanLength 4 ScanIn WSI ScanOut
WSO ScanCells wcell0..3 ScanMasterClock
WRCK Pattern pat1 P d0..400000
si0111000 si111110000 so0001X11
so1111100X1 q0..2001 P d0..401101
si0011010 si101011101 so01100X1
so110110000 q0..2110 P d0..411001
si0110010 si100011100 so0010001
so11X110100 q0..200X P d0..401010
si0001101 si110011101 so011X000
so1101110XX q0..2011 P d0..401111
si0010001 si110101101 so00X1111
so100001X10 q0..2000

• STIL 1.0
• Design A-26-2003
• TL 2004
• Header
• Title "Serial Intest"
• Date "2004"
• Signals
• WSI In DefaultState N
• se In DefaultState D
• clk In DefaultState D
• d0..4 In DefaultState N
• WPI0..2 In DefaultState N
• WPO0..2 Out
• q0..2 Out
• WSO Out
• WRSTN In DefaultState U
• SelectWIR In DefaultState D

22
Using CTL to construct the wrapper

• WS_INTEST_SCAN

23
Conclusion

• IEEE 1500 two important aspects of core-based SOC
  testing
• Core test knowledge transfer from core provider
  to core user by means of standardizing a Core
  Test Language
• Test access to embedded cores by means of
  standardizing a core wrapper that supports both
  core-internal and core-external testing.
• The flexibility and scalability to meet the
  requirements for a wide range of different cores
  and business models