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Cycle-true simulation of the ST10 microcontroller
including the core and the peripherals
Lovic Gauthier, Ahmed Amine Jerraya SLS group,
TIMA Laboratory 46, avenue Félix Viallet 38031
Grenoble cedex1 - France Lovic.Gauthier_at_imag.fr,
Ahmed-Amine.Jerraya_at_imag.fr
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Outline

• Introduction
• Context
• Motivation
• Goal
• Simulation methods
• The ST10 microcontroller
• The ST10 simulator
• Results and applications
• Conclusion

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Introduction context

• Current electronic systems
• Contain both hardware/software parts
• Are more and more complex
• Validation is a key problem
• The sooner the better (prototype validation is
  too late)
• It has to be fast (slow validation would take
  years)
• Co-validation is necessary

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Introduction motivation

• Software validation
• Functionality formal verification, native
  execution
• Timing ?
• Timing difficulties
• Strongly dependant on the processor
• Strongly dependant on the environment
• Hard to predict
• Solution for software timing validation
• Simulator of the processor executing the software

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Introduction goal

• Main goal
• Study of a working method for development of
  microcontroller simulators including the
  peripherals.
• Constraints timing validation of software
• Precision cycle-true for external events.
• Speed enough for complex simulation (few
  minutes of real time running in a few hours)
• Flexibility possible to integrate into a
  co-simulation environment
• Chosen microcontroller ST10 from
  STMicroelectronics

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Outline

• Introduction
• Simulation methods
• State of the art
• Our approach
• The ST10 microcontroller
• The ST10 simulator
• Results and applications
• Conclusion

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Simulating methods state of the art
? No method is good enough in each field
for hardware/software timing validation
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Simulating methods our approach

• Compromise between software HDL simulations and
  software ISS.
• Description/execution model of an ISS
  (programming language oriented) but

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Outline

• Introduction
• Simulation methods
• The ST10 microcontroller
• The ST10 simulator
• Results and applications
• Conclusion

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The ST10 Microcontroller

• 16 bits pipelined CPU core
• Standard interrupt handling, and PEC
• (Peripheral Event Controller)
• Customisable external Bus controller
• On-Chip RAM / ROM.
• Peripherals
• ADC 10 bits analog/digital converter
• CAPCOM 2 capture/comparison units
• PWM pulse width modulator
• GPT 2 general purpose timers
• ASC synchronous/asynchronous serial
• interface (USART)
• SSC high-speed synchronous serial
• interface
• WDT watchdog timer
• Optional peripherals (CAN, MAC )
• 9 customisable I/O ports

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Outline

• Introduction
• Simulation methods
• The ST10 microcontroller
• The ST10 simulator
• The ST10 simulator
• The model of the core
• The model of the peripherals
• The peripherals/core communications
• Results and applications
• Conclusion

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The ST10 simulator

• 3 parts
• Core simulator (IDL)
• Peripherals simulator (C)
• Main loop (C)
• Each step of the loop
• Execution of a cycle of the core
• Execution of a cycle of each peripheral
• I/O update

extern C reset() extern C do_cycle() ... int
main(argv, char argc) int
cycle,maxcycles reset()
Periph_ADC.reset() cycle0
while(cycle!maxcycles) do_cycle()
Periph_ADC.do_cycle() ...
cycle
Core (C)
C/C compiler
Peripherals (C)
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The ST10 simulator the model of the core (1)

• Described in IDL C-like language with specific
  constructions for
• ISS design.
• C code of the simulator generated by Flexsim

IDL description
C description

C functions provided
/ Instruction coding / / Global variables
/ pipeline ST10_instr st10pipe FE, DE, EX,
WB / Local variables / before /
Interrupt polling / stage FE /
Instruction fetch (FEmemPC)/ stage DE
/ Decode, operand fetch / stage EX
/ instruction execution / stage WB /
Write-Back to memory / / Memory mapping /
int reset() int do_cycle() int
read_register(int regnum) void
write_register(int regnum,int value) void
do_interrupt(int ITnum)
FLEXSIM
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The ST10 simulator the model of the core (2)

• Basic simulation schemes
• Registers ? IDL variables (bit field)
• Memory ? IDL array
• Instruction decode ? IDL switch/case specific
  for instruction
• Instruction execution ? IDL computation
• Parallelism
• Pipeline ? sequential execution of each stage
• By-pass ? moving parts that one to another stage
• Interrupts
• modelled by flags (bit variables) that are
  checked each cycle before
• executing the pipeline sequence

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The ST10 simulator the model of the peripherals
(1)

• Modelled peripherals
• ADC 10 bits analog/digital converter
• CAPCOM 2 capture/comparison units
• PWM pulse width modulator
• GPT 2 general purpose timers
• ASC synchronous/asynchronous serial interface
  (USART)
• SSC high-speed synchronous serial interface
• WDT watchdog timer
• External bus Controller
• 9 customisable I/O ports
• Described in C
• one class per peripheral
• C methods provided constructor, do_cycle

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The ST10 simulator the model of the peripherals
(2)

• Simulation of the control parts
• FSM implemented with a switch/case
• C structure.
• Simulation of the operative part
• Registers ? C variables
• Computation ? C expression
• Analog parts ? floating point numbers/fixed
  point numbers/integers
• (for the ADC 16 bits integers)

Periph_ADCdo_cycle() switch(state)
case state0 break case state1
break case state2 break ...

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The ST10 simulator the peripheral/core
communications

• Commonly two methods for microcontrollers
• Use of specific registers to exchange data
• Use of interruptions to indicate events
• Simulation at the end of each peripheral cycle
• Specific registers ? setting global variables of
  the core simulator
• representing the specific registers
• Interruption ? setting global variable of the
  core simulator
• representing the interrupt flags

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Outline

• Introduction
• Simulation methods
• The ST10 microcontroller
• The ST10 simulator
• Results and applications
• Application
• Evaluation
• Future work
• Conclusion

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Results and application Application

• Easy integration into a co-simulation
  environment
• Validation with hardware/software applications
  such as
• ST10 / Matlab (mechanic)
• ST10 / VHDL (electronic)
• multiple ST10 (multiprocessor architectures)

Cosimulation bus
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Results and application evaluation

• Simulator of the ST10 microcontroller including
  the peripherals
• Cycle true simulation of the ST10
  microcontroller including the core and
• the peripherals
• Core simulator
• up to 50000 instructions per second on a 167MHz
  Ultra Sparc station
• long to design and validate
• Peripherals simulator
• little overhead less than 20 of the global
  simulator runtime
• easy to design
• Easy to integrate into a co-simulation
  environment.

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Results and application future work

• It is possible to increase the speed of the core
  simulator
• New management scheme of the pipeline only
  simulating the external
• timing consequences ? avoid the complex
  computations of the
• dependencies between instructions
• Flags computation only when it is necessary.
• Speed up estimated 5 times faster (or more).

if (In1 does not compute the flags) or
(In1 need the flags) then compute the
flags for In end if
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Outline

• Introduction
• Simulation methods
• The ST10 microcontroller
• The ST10 simulator
• Results and applications
• Conclusion

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Conclusion

• The problem
• Hardware/software timing validation
• need of processor/microcontroller simulators
• Existing processor/microcontroller simulator
• does not combine all the features needed
• Our solution
• Intermediate microcontroller simulator between
  HDL
• simulators, and software ISS.
• Peripherals are include, cycle-true, fast
• Core model is long to design, peripheral model
  is easy to design
• Validation with co-simulation applications