Presentation to Taiwan SoC Consortium Visitors (2002-06-06, Kista-Stockholm) SoC Education and Interconnect-Centric SoC Design at KTH

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Presentation to Taiwan SoC Consortium Visitors
(2002-06-06, Kista-Stockholm) SoC Education and
Interconnect-Centric SoC Design at KTH
Dr. Li-Rong Zheng (??? ??) Laboratory of
Electronics and Computer Systems Royal Institute
of Technology (KTH) SE-164 40 Kista-Stockholm Swed
en E-mail lrzheng_at_imit.kth.se URL
http//www.imit.kth.se/lrzheng
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KISTA SCIENCE PARK is number two in the world
In July 2000 Wired Magazine presented its latest
ranking concerning global science parks which
placed Kista Science Park on second place
together with Boston and Israel. Kista Science
Park is a strong contender for the title of being
the European version of Silicon Valley. Cross
fertilization between companies, research
development and schools of higher education
continually generate new ideas. This is the
driving force of increasingly rapid development
of IT companies within KISTA SCIENCE PARK. KISTA
SCIENCE PARK is situated in northwestern
Stockholm. Today KISTA SCIENCE PARK nourishes
some 700 companies, 28 000 employeés and 3 300
students at university level.

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The IT University in Kista - A "virtual"
university
The IT University is the common name for all
academic activities in Kista / Stockholm. It is a
joint venture between KTH (the Royal Institute
for Technology) and Stockholm University as
partners. Karolinska Institutet (the medical
university) becomes partner in the venture from
fall 2001.
Central Function Vice-President for Academic
Affairs Prof. Gunnar LandgrenDean Prof. Hannu
TenhunenVice-Dean Prof. Björn Pehrson
Departments Department of Microelectronics and
Information Technology (IMIT) Department for
System and Computer Science (DSV) Department of
Applied Information Technology Centers KTH
Online KTH Semiconductor Laboratory (Central
Clean Room) Swedish Center for Internet
Technology KTH Center for Wireless Systems
Figures from 1999. (Aprox.) Undergraduate
fulltime 2 500 Students total 3
500 Researchers 140 No. of employees 440 Turn
over MSEK 400
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Campus Kista
Electrum Isafjordsgatan 22
Ingenjörsskolan
Electrum
Forum
Ingenjörsskolan
Forum Isafjordsgatan 39
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Department of Microelectronics and Information
Technology (IMIT)

• The new department is organized in five labs, two
  sections, and two centers
• Laboratory of Materials and Semiconductor
  Physics
• Laboratory of Solid State Devices
• Laboratory of Optics, Photonics and Quantum
  Electronics
• Laboratory of Electronics and Computer Systems
• Laboratory of Communication Networks
• Section for Telecommunication Systems
• Section for Wireless Systems
• KTH Online
• Semiconductor Laboratory
• The Department of Microelectronics and
  Information Technology was formed January 1st
  2001 by merging the following departments and
  groups
• Department of Electronics (see this page for
  links to individual groups)
• Department of Teleinformatics (see this page for
  links to individual groups)
• Section of Materials Physics (Dept. of Physics)
• Section of Condensed Matter Physics (Dept. of
  Physics)
• Section of Optics (Dept. of Physics)
• KTH Online
• Semiconductor Laboratory

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Laboratory of Electronics and Computer Systems
(LECS)
Research groups Prof. Hannu Tenhunen,
Electronic Systems Design (ESD) Prof. Håkan
Olsson, Radio and Analog Electronics (REL) Prof.
Seif Haridi, Distributed Computer Systems
(DCS) Prof. Mats Brorsson, Computer Theory and
Engineering (CTE) Prof. Axel Jantsch, System
Architecture and Methodology (SAM)
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LECS Activities
Co-operation with industry
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LECS Research
Parallel and Distributed Systems
Software aspects
Performance Evaluation of Computer Systems
Distributed Computer Systems
Computer Architecture
System Architecture and Methods
Electronic System Design
Radio Electronics
Circuits and Devices
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System Simulation/Emulation and Prototyping
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SoC Education StrategiesInternational Master
Program on System-on-Chip Design
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System-on-Chip int. M.Sc. Program Socware
Engineering
www.ele.kth.se/SoC/
www.socware.com
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New competence profiles needed

• IT-services and end-user behaviour
• Distributed and parallel processing
• Networking and protocols
• Digital communication and multimedia
• Software engineering
• Computer architectures adn compilers

• Embedded systems
• CASE/EDA/CAD
• VLSI systems and circuit design
• RF/analog/mixed signal IC desiign
• Semiconductor technology
• Electronic and system packaging

Challenge New breed of students than our
generations
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About the SoC Master Program

• Globally the first master program on SoC,
• start from 2000
• Students from worldwide
• (Asia, Europe, African, S/N America)
• Minim. Requirement
• English (TOEFL 550/213, IELTS 5.5, TWE 4.5)
• Degree BS/BE in EE, CS, CE (gt120 CU)
• Number of students
• 2000 23 4 KTH (3 to Ph.D. study), 3 abroad, 15
  industrial, 1 drop out
• 2001 43 15 KTH, 15 industrial, 12 abroad, 1
  drop out
• 2002 65 start from Sept.2 2002
• 40 CU courses (24 oblig. 16 optional), 20 CU
  thesis
• More information at www.imit.kth.se/SOC

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Main Courses for SoC Master
 
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Different abstraction views in the curriculum

• Physical/Implementation view where the relevant
  features of technology are handled at different
  abstraction levels.
• Functional view where the proper abstract
  architectures and interfaces between different
  architectural elements are explored.
• Methodology view where the supporting design
  processes and organizational workflows, such as
  concurrent engineering, is covered for efficient
  and high quality execution of the design tasks.

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Researches inElectronic System Design Group
Head Prof. Hannu Tenhunen Faculty Dr.
Svante Signell (Ericsson Radio System) (Mixed
signal SoC and DSP) Dr. Elena Dubrova (Logic
synthesis, fault tolerance in SoC) Dr. Ana Rusu
(ADC converter and mixed signal) Dr. Li-Rong
Zheng (Interconnect centric SoC design and
System-on-packaging)
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On-Going Research Projects

• Wideband Sigma-Delta A /D Conversion Techniques
• COBRA- Data Converters for Broad Band Radio
  Systems
• System-on-Chip for Mobile Internet
• Wafer Level Packaging and Single Level Integrated
  Packaging Modules for High Frequency Wireless
  Communication Devices
• Concurrent Packaging and VLSI Design for
  High-Frequency Circuits and Systems
• Innovative RF/HF Blocks in System-on-Packaging
  Integration for Multi-band Multi-standard Radio
  Applications
• Mixed Signal Design for System-on-Packaging
  Integration

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On-Going Research Projects

• Interconnect-Centric System-on-Chip Design for
  Network-on-Chip
• Communication Platform Architectures for
  Gigascale Integration
• Processor performance modeling
• Low power DSP integration
• Noise and interference analysis of mixers
• Sampling architectures for software controlled
  receivers
• Probabilistic Verification methodology for DSP
  ASICs
• Level-Limited Optimization of Digital Logic
  Circuits
• New Data Structure for Design Automation of
  Complex Systems
• Fault Tolerance in System-on-a-Chip
• NanoEDA Architecture and design methodology for
  nano-scale electronic systems

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Interconnect Strategies
Global operation Low bandwidth High latency
High power The length increases
20 clocks
Semi-global operation (between)
90,000 tracks
Local, parallel operation high bandwidth Low
latency Low power The length scales down
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Project Example Interconnect Centric SoC Design
1 clock
High Performance, small resource size
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Physical Performance Estimation
Wire Distribution Models 1. Rents Rule 2. J. A.
Davis, IEEE Trans. Electron Devices, vol.45,
pp.580-589, 1998 3. J. P. Krusius, IEEE Trans.
Adv. Packaging, vol.22, no.4, pp.642-648, 1999,
NOCs alleviate the wring demand.
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Research example Power distribution for SoC
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Example Early Estimation of Physical Performance
0.18um CMOS with 6 metal layers M5 M6 Planned
for power distribution Power Noise lt 10
Vdd (result 25 of M5 and M6) Global
signal clock distribution (result 75) M3
M4 Semi-global wires M1 M2 Local wires Result
of Crosstalk lt 20dB if f lt 1GHz Result of
Critical wire delay result 7.19 gate delay
(M6)
A priori power supply noise estimate. (169-pin
C4-bonded multi-layer ceramic PGA package. 0.18mm
CMOS, 6 Metal Layers).
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Project Example Interconnect Centric SoC for
Network on Chip
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Project Example Mixed Signal Implementation
SoC or SoP
(1) Signal transmission and signal integrity
(2) System-timing and system performance (3)
Chip I/O design and power distribution (4)
Optimized system partitioning and system
performance
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SoC vs. SoP
Everything is about Cost and Performance, and
also Time-to-Market, then the implementation

• Definition of a system
• Complete Functionality
• Minimum I/Os
• Hardware/Software
• Mixed-signal (RF, analog, digital MEMS,
  optical)

• Cost Performance
• System Performance
• Cost for heterogeneous integration
• Cost for mixed-signal isolation
• Technology fusion
• Intellectual property protection

1 1 lt 2?
1 2 gt 3?
System-on-Chip
system-on-package
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For Further Information and Publications
http//www.imit.kth.se/LECS Or e-mail to
lrzheng_at_imit.kth.se