SimulinkBased MPSoC Design Flow: Case Study of MotionJPEG and H'264

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Simulink-Based MPSoC Design Flow Case Study of
Motion-JPEG and H.264

• Kai Huang 1, Sang-il Han 2, Katalin Popovici 3,
• Lisane Brisolara 4, Xavier Guerin 3, Lei Li 1,
  Xiaolang Yan 1,
• Soo-Ik Chae 2, Luigi Carro 4, Ahmed Amine Jerraya
  5
• 1 Institute of VLSI Design, Zhejiang University,
  China
• 2 Seoul National University, Korea
• 3 TIMA Laboratory, France
• 4 Federal University of Rio Grande do Sul, Brazil
• 5 CEA-LETI, MINATEC, France

44th Design Automation Conference (DAC 07)
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Motivation
System level design Key solution to complex MPSoC

• Algorithm/Architecture mapping (System Level)
• Protocol Accurate (Virtual Architecture Level)
• Synchronisation Accurate (Transaction Level)
• Cycle Accurate (Virtual Prototype Level)

Application

• SystemC

• A preferred HW/SW codesign language

• Within a wide range of abstraction levels

• Intrinsic low level language
• NOT easy to specify the complex system at
  algorithm level

• Simulink

Physical implementation

• The prevailing environment
• Modeling and simulating complex systems at
  algorithm level

• An open issue Algorithm/Architecture mapping for
  MPSoC

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Objective

• 1) System level MPSoC design flow

• Combine Simulink with SystemC
• Simulink for high-level algorithm/architecture
  modeling
• SystemC for low-level HW/SW design
• Higher Level programming model
• Seamless refinement at different level
  abstraction models
• Systematic and automated SW generation
• Architecture and or Mapping experimentation

• 2) Case study for multimedia applications
• Feasibility and efficiency of proposed design
  flow
• System functional validation
• Performance analysis
• Guide for architecture exploration.

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Content

• Motivation Objective
• Proposed MPSoC Design Flow
• Overall Design Flow
• HW and SW Mixed Model
• Case Study
• Motion-JPEG Decoder
• H.264 Baseline Decoder
• Conclusions Future Works

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Overall Design Flow
Application
Architecture
Mapping
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Architecture/Alogoritm Mapping Simulink
HW Lib
SW Lib
HW Gen
SW Gen
.
.
Virtual Architecture
Transaction level
Virtual Prototype
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HW and SW Mixed Models

• Seamless refinement at four abstraction levels
• Simulink Combined Algorithm and Architecture
  Model (Simulink CAAM)
• HW/SW Interfaces refinements

HW-SW Codesign
OS and HW codesign
Target CPU Design
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Content

• Motivation Objective
• Proposed MPSoC Design Flow
• Overall Design Flow
• HW and SW Mixed Models
• Case Study
• Motion-JPEG Decoder
• H.264 Baseline Decoder
• Conclusions Future Works

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Simulink CAAM of M-JPEG Decoder

• Three CPUs (ARM, Xtensa)
• Communication Units (GFIFO, HWFIFO, SWFIFO)

7 S-Functions 7 Delays 26 Links 4 IASs
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Experiment Results of MJPEG

• 10-frame QVGA (320x240) JPEG stream

• RTW sequential program on the host machine
• Simulink Simulation in Simulink GUI
• VA System C model without HW information
• TA Abstract CPU Other devices (SC TLM)
• VP Cycle Accurate ISS Other devices (SC TLM)

Three ARM7 Subsystems
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Performance Analysis of MJPEG Experimental Results

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Experiment Result of H.264 Baseline Decoder with
10-frame QCIF Foreman
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Conclusions Future Works

• Proposed a Simulink based MPSoC design flow
• For automated concurrent hardware-software design
  and verification
• Simulink to Model Algorithm/architecture mapping
• SystemC for lower abstraction level models (VA,
  TA, VP)

• In the case of Motion-JPEG decoder and H.264
  decoder
• The feasibility and efficiency of proposed design
  flow
• Functional evaluation
• Performance analysis
• Guide for architecture exploration

• Plan to improve the current design flow
• Dedicated instruction sets
• Communication protocol with DMA
• Automatic design space exploration

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Thanks for your attention !