Memory Level General Subgroup CTL Modeling

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Memory Level General SubgroupCTL Modeling
Update

• May 11, 2007

Confidential
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Memory Level General

• Members
• Mouli (Leader), Jay, Karen, Geir
• Scope
• Define CTL constructs to describe the Memory
  Level Information excluding Address/data mapping,
  Redundancy and Memory Access Mechanism
• Milestone VTS2007 ( Delayed)

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Memory Level GeneralInitial List

• Memory Type
• SRAM, DRAM, ROM, FLASH, Single Program ROM, CAM
• Synchronous, Asynchronous
• Memory template Name
• Logical Ports(x)RW, (y)R, (z)W, (m)M(Match
  ports)
• Port synchronicity
• Retention Time
• Bypass Mode
• Memory Timing (can we make it more general that
  provide all timing information on the memory. May
  be in the form of a wrapper, would also include
  ADT.)
• Write Mode Operation (Select During Write
  Through)
• Data Input/Out Stages
• Flop, Latch, None
• Number of stages
• Count Ranges for Bank, Row, Column
• _ Tri State condition

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What Memory Attributes are Covered

• Memory Functional Architecture
• Describe memory functionality for various memory
  types at the I/O level
• Eg., Read/Write/Write-through/Write-back
  Operations
• Memory Test Architecture
• Testing the memory core
• Describe the data/address/control signals needed
  to test the memory core
• Testing shadow logic
• Describe all signals (I/O level) that enable
  shadow logic test

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Memory Functional ArchitectureAttributes

• Memory Structure
• Memory Functions ( Are these covered by access
  or Pin function sub groups)
• R/W behaviour
• Multiport contentions
• Write-back, Write through operations

Input Address Lines Data Lines Enables
(R/W, CEN, ...) R/W, M ports
ClocksRegistered inputs
Memory Type SRAM/ROM/DRAM/FLASH/CAM Synchronous
/AsynchronousPipelined/Non-pipelinedColumn
Muxbanks/rows/columnsRetention time
Output Data LinesTristate condition
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Memory Test Architecture Attributes

• Test Structure
• Test Functionality ( covered by other sub
  groups?)

Input Test Mode signals(Memory BIST, Logic
BIST, ATPG) Bypass Mode signals ( asynch,
synchronous) Test Data, Address, Control
signals ( for shadow logic test) Other Test
Modes ( margins, bit-cell variabilities, etc)
Memory Core
OutputTest result signals( Done, Error, Test
Data)
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Sample Template for Memory General Attributes
STIL 1.0 CTL 2005 Design 2005 Variables
IntegerConstant maxdata
IntegerConstant maxaddr IntegerConstant
addrmax Signals / AddressRange, Data
Range, Controls in Data Range out Test
address Range, Test Data Range out Test
Control Range out / . . Environment
CTL Memory Properties
/ ( define rows/bank, CM, synch/asynch,
R/W port contentions) /

CTL Mission Mode Test Mode
Normal Family (DRAM/SRAM/ CAM/
Flash/ROM) Internal /
define all the signals /
CTL BIST_mode
TestMode Internal Test Internal
/ define all the signals /
CTL Bypass_mode
TestMode Bypass Internal
/ define all the signals /

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Schedule Milestone
Milestone Date
Complete definition of Memory functional attributes 6/30/07
Complete definition of Memory Test attributes 7/15/07
Complete CTL model for memory functional attributes 8/15/07
First draft of CTL model for memory general functionality 9/15/07
Review of first draft 10/1/07
Final draft 10/15/07