Front End Driver (FED) Crates and Racks Tracker PSU racks

1
Front End Driver (FED) Crates and RacksTracker
PSU racks

• Matthew Pearson
• RAL
• m.pearson_at_rl.ac.uk

Electronics Week November 2002
2
Considerations

• How many FEDs per crate?
• How shall we arrange the FEDs?
• Dont mix FEDs from different partitions
• In crates?
• In racks?
• Separate into /-?
• Do we need to reserve space in case we need to
  use more
• FEDs than we expect? (if data rate per FRL is
  gt200Mbytes/s)
• Can we keep the S-LINK64 short enough?
• (Has to be less than 15m)

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How many FEDs per partition?

• 440 FEDs in total
• 4 Partitions TEC, TEC-, TIBTID, TOB
• Partition Layer
  FEDs
• TEC (1-3,4-6,7-8,9)
  (40,32,16,8) 96
• TEC- (1-3,4-6,7-8,9)
  (40,32,16,8) 96
• TIBTID 2(1,2,3,4)2(1,2,3) 2(12,16,6,8)
  2(5,5,5) 114
• TOB 2(1,2,3,4,5,6)
  2(11,12,7,8,14,15) 134
• Whats the best way to arrange these?
• Note Data rate per FED is highest for TIB1 and
  TEC7,8,9

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How many FEDs per crate?

• VME64 crates have 21 9U slots (see reference 1)
• 17-19 FEDs per crate ---- Depending on
  other
• 
  modules used.

• Other modules
• Spare slots (eg. Tester board)
• 1 or 2 less slots in each crate
• FMM (Fast Merging Module)
• Or something similar, which may
• be a transition card on the back-plane.
• 1 less slot in each crate (?)
• Crate or rack controllers?
• 1 less slot in each crate

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Crate/Rack Controllers

• Remote PC based crate controllers are favoured.
• Need VME interface module in each crate
• Interface module has to be 6U

A 6U module needs 6U-9U adapter. (only takes up
one slot)
VME Backplane
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Number of crates
Assume a given crate contains FEDs from only 1
partition. If 17 or 18 FEDs per crate
Partition Crates TEC
6 TEC- 6 TIBTID
7 TOB 8
For 19 FEDs per crate
Partition Crates TEC
6 TEC- 6 TIBTID
6 TOB 8
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How many racks?

• Dont mix partitions in a rack.
• Partition Racks
• TEC 2
• TEC- 2
• TIBTID 3
• TOB 3
• TOTAL 10 racks
• true for both 17 or 18
• FEDs per crate.
• for 19 FEDs per crate we
• save one rack.
• also, dedicated DAQ racks for each partition (64
  FRLs per DAQ rack).

3 crates per rack
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Suggested FED rack layout
1.0m 1.5m
A B C

• Need PC racks for
• FEDs and DAQ
• FED racks are grouped
• to assist in cabling
• (Francois)
• Each DAQ is close to
• FEDs from same
• partition

1 DAQ DAQ
2
TIBTID TOB 3
TIBTID TOB 4
TIBTID TOB 5
DAQ DAQ 6
FED PCs DAQ 7
DAQ DAQ 8
TEC- TEC 9
TEC- TEC 10
TEC- TEC 11
12 13 . .

S-LINK length minimised (lt10m)
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TIBTID Crates
Assuming 17 FEDs per crate (The number of FEDs in
each crate is shown in brackets)
FRLs
FRLs
TIB2 (16)
TID2 (5)
TIB1 (12)
TID2- (5)
TIB2- (16)
TIB3 (12)
TIB1- (12)
B5
B1
B2
B4
B3
10
TOB Crates
FRLs
FRLs
TOB2 (12)
C2
C3
C4
C5
C1
11
TEC/- Crates
FRLs
C7/B7
C9/B9
C10/B10
C8/B8
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S-LINK64 cable length

• The S-LINK64 standard will be used for the
  FED-FRL connection.
• If using S-LINK PCI source card on VME transition
  card,
• the link runs at 66MHz.
• This has been shown to be OK for cable
  length of 15m.
• Therefore
• the S-LINK cable lengths between FEDs and
• FRLs of lt10m are OK.

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Some other S-LINK points

• We would like to run FED at 40 or 80MHz (320 or
  640Mbytes/s).
• For convenience
• To run as fast as possible
• (to cope with unexpected high data rates)

• If FED runs at 80MHz, we will get back-pressure
  signals from the S-LINK source card.
• An alternative is to drive the S-LINK directly
  from the FED FPGA.
• We could then run at any speed up to 100MHz (the
  S-LINK standard limit) but would prefer to run
  at 80MHz
• This would place tighter restrictions on the
  S-LINK cable length. How much tighter?????

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Tracker PSU racks
Current base-line plan is to place TK PSUs in
the Experimental Hall (UXC55).

• 20 racks for SST
• 2 racks for Pixel
• 4 racks for 48V DC PSUs

(estimates from Horst)
Allocate space

• 29 racks on Upper Balcony in central position
• 24 racks on Middle Balcony in central position

Still things to consider (accessibility,
maintenance, cost, radiation and magnetic field
issues ...)
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Summary

• A scheme has been presented detailing the FED
• layout within the crates and racks, and the
  placement
• of the racks in USC55.
• Note
• If the scheme is approved, and once the cables
• are cut by Francois, nothing can be changed.

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References

• Technical specification for subracks for LHC
  experiments
• http//atlas.web.cern.ch/Atlas/GROUPS/FRONT
  END/rackscrates.html
• 2. The S-LINK 64 bit extension specification
  S-LINK64
• http//his.web.cern.ch/HIS/s-link/spec/
• 3. CMS DAQ Technical Design Report
• 4. Rack layout in USC55
• http//cmsdoc.cern.ch/wsmith/USC55_racks_v3
  6.html