Decision-directed Joint Tracking Loop for Carrier Phase and Symbol Timing in QAM

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Decision-directed Joint Tracking Loop for Carrier
Phase and Symbol Timing in QAM

• Project 2
• ECE283
• Fall 2004

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Outline

• System concept
• QAM signal source and receiver
• Decision-directed PLL
• Characterization
• Tools
• Submission

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System Concept (1)
Simplified 64-QAM communications system
64-QAM demodulated with perfect phase and 2.5
phase lag
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System Concept (2)
Receiver
Transmitter
QAM receiver system
QAM communication system
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QAM Signal Source and Receiver
QAM receiver
QAM transmitter
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Decision-directed PLL
Decision-directed PLL system diagram
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Complete System
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PLL Output (1)
Phase locking performance with a random QAM
waveform
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PLL Output (2)
Phase locking with 10 deviated frequency signal
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PLL Tuning

• Modulation frequency
• Number of waves per symbol
• LPF
• VCO and VCC
• Symbol feedback delay

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Characterization

• Waveforms
• Timing error (RMS)
• Capture range
• Loop lock range
• Effect of symbol error
• Effect of signal noise
• And more

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Tools

• A Continuous-time simulation tool
• Simulink is recommended
• Circuit-level simulation ?

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Submission

• Files All files should be in lastname_firstname
  directory and the directory should be compressed
• Document IEEE journal format, ps or pdf,
  lastname_firstname.ps/pdf
• Source Files One-step testable codes with
  appropriate waveform output scopes
• Deadline 1100pm, 10/15 Friday, time marked by
  receiving mail server
• Email dkim_at_ee.duke.edu