WorstCase Analysis to Obtain Stable Read Write DC Margin of High Density 6TSRAMArray with Local Vth

1
Worst-Case Analysis to Obtain Stable Read / Write
DC Margin of High Density 6T-SRAM-Array with
Local Vth Variability

• Y. Tsukamoto, K. Nii, S. Imaoka, Y. Oda,
• S. Ohbayashi, T. Yoshizawa, H. Makino,
• K. Ishibashi and H. Shinohara
• E-Mail tsukamoto.yasumasa_at_renesas.com

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Outline

• Introduction
• Concept of Vth Curves
• Worst Case Model of Read Margin
• Vth Curves for 65 nm SRAM
• Conclusion

3
Introduction 1.

• Vth Variability Issue
• Global Variability( sGlobal )
• Depends on Lg, Tox, etc.
• Varies Die to Die, Wafer to Wafer, Lot to
  Lot
• Local Variability( sLocal )
• Depends on dopant fluctuation, Gate LER,
  etc.
• In proportion to (LW)-1/2

sVth2 sGlobal2 sLocal2
Scaling degrades Local Vth Variability
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Introduction 2.

• 6T-SRAM is sensitive to Vth variability due to
  use of small L/W transistors.

WL
LD1
LD2
AC1
AC2
DR1
DR2
BL
BLC
Equivalent Circuit of Single Port 6T-SRAM
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Introduction 3.

• Global and Local Variability effect on SNM

With Global
With Local
SNML
SNML
Left Storage Node V
Left Storage Node V
SNMR
SNMR
Right Storage Node V
Right Storage Node V
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Introduction 4.
Purpose of this work To examine the Vth
boundary within which the SRAM read / write DC
margin can be guaranteed to exist despite large
local Vth variability.
7
Outline

• Introduction
• Concept of Vth Curves
• Worst Case Model of Read Margin
• Vth Curves for 65 nm SRAM
• Conclusion

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Concept of Vth Curves 1.

• Vth Condition and SRAM DC Margin

WL
Vth effect on DC Margin
LD1
LD2
AC1
AC2
DR1
DR2
BL
BLC
Global Variability
NMOS
PMOS
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Concept of Vth Curves 2.

• Visualization of Vth Condition for SRAM DC Margin

Read Fail
Read Boundary
Typical Vth
Typical Vth
With local
With local
R/W Pass Region
PMOS Vth (Vtp)
PMOS Vth (Vtp)
R/W Pass Region
Write Boundary
Write Fail
NMOS Vth (Vtn)
NMOS Vth (Vtn)
If we obtain the exact boundaries (Vth curves) ,
we can optimize the typical Vth condition to
achieve a stable read / write operation.
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Concept of Vth Curves 3.

• How do we determine Vth curves?

STEP 1. With Global
STEP 2. With Local
Select Random Points around A0
Introduce global var. to TYP-Vth
Vtp
Vtp
450
450
A0
A0
TYP-Vth
TYP-Vth
50
50
400
400
- 50
- 50
Vtn
Vtn
500
450
500
450
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Concept of Vth Curves 4.

• Estimate SNM at point B0 and judge.

SNM at Point A0 B0
STEP 3. Estimate SNM
B0Minimum SNM point
Vtp
B0
Left Node V
450
A0
TYP-Vth
50
400
- 50
Right Node V
Vtn
Judge If SNM 0 at B0, A0 is on the Vth
curve
500
450
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Concept of Vth Curves 5.

• Obtain Several Points on Vth curve

Repeat Step.1 Step.3
B2
Change the coordinates (-50, 50), and examine
SNM around A1, A2.
A2
Vtp
B0
450
A0
B1
TYP-Vth
50
400
- 50
A1
By connecting A0, A1, A2, we can obtain a Vth
curve.
Vtn
500
450
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Outline

• Introduction
• Concept of Vth Curves
• Worst Case Model of Read Margin
• Vth Curves for 65 nm SRAM
• Conclusion

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Worst Case Model of Read Margin 1.

• Local Vth combination to be considered

How do we select this local Vth set?
Numerical Monte Carlo etc. Analytical Worst
Case Model
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Worst Case Model of Read Margin 2.

• SNML sensitivity to Each Cell Transistor Vth

AC1 and LD2 do not affect SNML.
1.5
SNML is a function of AC2, DR1, DR2 and LD1.
1.0
0.5
LD2
LD1
AC1
AC2
DR1
DR2
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Worst Case Model of Read Margin 3.

• SNML sensitivity to Each Cell Transistor Vth

Define Vth set of local components in units of s.
1.5
x sva for AC2 y svd for DR1 z svd for DR2 t
svl for LD1
1.0
0.5
Worst Vector (x, y, z, t)
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Worst Case Model of Read Margin 4.

• Worst Case Model for SNM

Defined by SPICE Model
Choose Arbitrarily
Local Vth Variability (assumed to be given)
sva, svd and svl obey (LW)-1/2 law
Aim
To obtain the Worst Vector ( x, y, z, t ) that
minimizes SNM
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Worst Case Model of Read Margin 5.

• Introducing the concept of yield

2D-Image
r Probability ? Yield
r 6 90 Yield (50M-SRAM)
B
Vtp
r
x2 y 2 z 2 t 2 r 2
450
A
x r sin x sin j cos q
TYP-Vth
400
y r sin x sin j sin q
z r sin x cos j
t r cos x
Vtn
500
450
Distribute 6s Probability to 4 Transistors
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Worst Case Model of Read Margin 6.

• Mathematical Expansion

Taylor Expansion
2D-Image
B
SNML(B) SNML(A)S
Vtp
r

• SNM

ksvi
450
?(tsvi )
A
i
TYP-Vth
i ac, dr, ld
400
k x1, y1, z1, t1 (Purpose)
t x0, y0, z0, t0 (initial)
Vtn
500
450
Expand SNM function to the first order
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Worst Case Model of Read Margin 7.

• Deriving Differential Equations

Differential Equation
2D-Image
B
Vtp
r
q
450
A
TYP-Vth
400
Vtn
500
450
?SNM should be 0 for small change of ?, ? and ?.
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Worst Case Model of Read Margin 8.

• Solve the Differential Equations

Analytical Solution
A is a normalized factor
We can derive the Worst Vector (xn, yn, zn, tn),
iteratively.
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Worst Case Model of Read Margin 9.

• Comparison with Result Using Numerical Analysis
  (Multiple Linear Regression Analysis)

• By deriving the worst vector iteratively, we can
  get close to the numerical result.
• The SNM for 4th order iteration is within 1mV.

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Outline

• Introduction
• Concept of Vth Curves
• Worst Case Model of Read Margin
• Vth Curves for 65 nm SRAM
• Conclusion

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Vth Curves for 65 nm SRAM 1.

• Simulated Vth Curves

Cell Transistor WACWDRWLD 11.41 Target
Yield 90 for 50Mbit (r 6)
Read Vth Curve
Simulation Condition Vdd 1.2V Temp 27
deg. sLocal (DR) 40 mV 4th Order Iteration
PMOS Vth ( Vtl ) A.U.
Typical Vth
Write Vth Curve
Typical Vth is in the R/W pass region.
NMOS Vth ( Vtd ) A.U.
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Vth Curves for 65 nm SRAM 2.

• Temperature Dependence

Cell Transistor WACWDRWLD 11.41 Target
Yield 90 for 50Mbit (r 6)
Solid Read Dashed Write
- 40 deg C
Simulation Condition Vdd 1.2V Temp - 40, 27,
80 deg. sLocal (DR) 40 mV 4th Order Iteration
Typical(L.T.)
PMOS Vth ( Vtl ) A.U.
80 deg C
Typical (R.T.)
- 40 deg C
Typical (H.T.)
Read Worst High Temp. Write Worst Low Temp.
80 deg C
NMOS Vth ( Vtd ) A.U.
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Vth Curves for 65 nm SRAM 3.

• Supply Voltage (Vdd) Dependence

1.32V
Cell Transistor WACWDRWLD 11.41 Target
Yield 90 for 50Mbit (r 6)
Solid Read Dashed Write
1.2V
1.08V
Simulation Condition Vdd 1.2V 10, -10 Temp
27 deg. sLocal (DR) 40 mV 4th Order Iteration
1.08V
PMOS Vth ( Vtl ) A.U.
1.2V
1.32V
Lowering Vdd by 10 has impact on
variability margin.
NMOS Vth ( Vtd ) A.U.
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Conclusion

• We have shown a new methodology for analyzing
  SRAM read/write margin in the presence of large
  local Vth variability.
• The analogy using Vth curves helps us to see the
  appropriate Vth condition to achieve high-yield
  SRAM.
• To obtain Vth curves, we introduced the worst
  case model for treating local variability, and
  derived the worst vector iteratively that
  minimizes SRAM DC margin.
• Applying this analysis to an SRAM cell in 65 nm
  technology, we demonstrated characteristic
  behaviors of Vth curves.