Interrupt Details and Resets

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Interrupt Details and Resets
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Using Interrupts with the Axiom Board

• Interrupt setup
• Write handler location into interrupt vector
• For IRQ, handler is at FFF2

• The issue
• FFF2 (and the entire IVT) is in the EPROM space
• Have to reprogram chip to change vectors

• The solution
• Axiom has pre-programmed all vectors to point to
  locations in RAM
• Modify that location to jump to your routine

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Axiom Interrupt Vectors
Change JMP target to the start of your handler
No jump table entry for reset.
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Using the Axiom Pseudo-Vectors

• Alter the pseudo-vector for your interrupt to
  jump to your handler

• Example Change IRQ pseudo-vector to point to
  IRQ_HANDLER

org 00EE jump table entry for
IRQ jmp IRQ_HANDLER jump to IRQ
handlerIRQ_HANDLER handler for
IRQ rti end of IRQ handler
WARNING This method is specific to Axiom boards
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Resets

• Resets are similar to interrupts, except
• They dont save any state
• Their vectors must be in ROM

• Resets initialize the state of the system
• Initialize SP, control registers
• Power-on reset
• Manual reset

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HC11 Reset
Open-draindriver on output
VDD
Reset is both an input and an output (open-drain)
HC11
4.7KW
reset
Low voltage reset circuitry- 34064 asserts
reset whenever input voltage is less than 4.6V
10mF
This prevents overwriting EEROMaccidentally
ResetSwitch
Capacitor to lengthenreset pulse
Reset must be asserted for at least 4 E clock
cycles tobe recognized by the MCU
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Other Resets

• Power-on reset
• When power comes on, resets the CPU
• Delays for 4064 cycles before starting operation

• COP watchdog
• Timer counts cycles
• If it expires (16ms - 2s, programmable), the a
  COP reset is issued
• Software must clear the timer periodically (see
  book for details)

• Clock monitor
• If clock isnt changing, causes a reset

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Low-Power Modes

• The HC11 has two low power modes to save energy
  when nothing is happening
• Wait - Entered by executing the WAI instruction
• Stops everything except the clock
• Waits until an interrupt or Reset is received
• Pre-stacks registers so interrupt response is
  faster

• Stop - Entered by executing the STOP instruction
• Stops even the clock
• Power down to a few microamps
• Waits for Reset, XIRQ, or IRQ

PWR Supply Current _at_ 2MHzMode Current Run,
Single-Chip 15 mA Run, Expanded 27 mA Wait,
Single-Chip 6 mA Wait, Expanded 10 mA Stop 0.025
mA
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Issues with external inputs

• A typical external interrupt input is a push
  button
• Push the button- get an interrupt

• Probems
• Contact bounce
• May need to debounce switch

• Button may be pressed longer than the interrupt
  handler runs
• Causes multiple interrupts

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Switch Debouncing
Input
GND
Out
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Switch Depressed
OutIdeal
OutActual
Switch Released
R-S LatchR S Output0 0 Unchanged0 1 1 1 0 0 1
1 Undefined
SPDT Switch
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Software Debouncing

• When interrupt handler is entered, pause (in
  software) for a little bit to allow switch to
  settle
• Advantage - no hardware needed

• Disadvantage - must delay while in the interrupt
  service routine Slows down user response

• Also fixes the problem of the interrupt handler
  finishing while the switch is still held down (if
  delay is long enough)
• May repeat after delay (this could be good)

Although SW debounce is tempting, very few
designers use it more than once
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Edge triggering

• Wed like to see one interrupt per button press
• Edge triggering can help us...

IRQ
Requires a clearoutput from CPU
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Q
D
clr
From CPU
From debounced button
Button
IRQ
clr
IRQ handler runs
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Edge Triggered Interrupt Inputs

• Edge triggering is great
• The HC11 allows us to configure the IRQ input as
  edge-triggered
• Must do so within first 64 clock cycles of
  operation
• Default is level-sensitive
• We cant change it unless we rewrite the monitor

• The three timer input capture inputs can be set
  to be edge-triggered, though...