RF Triangulator: Indoor/Outdoor Location Finding 18-525 Architecture Proposal Giovanni Fonseca David Fu Amir Ghiti Stephen Roos Design Manager: Myron Kwai - PowerPoint PPT Presentation

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RF Triangulator: Indoor/Outdoor Location Finding 18-525 Architecture Proposal Giovanni Fonseca David Fu Amir Ghiti Stephen Roos Design Manager: Myron Kwai

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Title: RF Triangulator: Indoor/Outdoor Location Finding 18-525 Architecture Proposal Giovanni Fonseca David Fu Amir Ghiti Stephen Roos Design Manager: Myron Kwai


1
RF Triangulator Indoor/Outdoor Location
Finding 18-525 Architecture Proposal Giovanni
FonsecaDavid FuAmir GhitiStephen RoosDesign
Manager Myron Kwai
  • Overall Project Objective
  • Design a Radio-Frequency indoor/outdoor
    navigation system, utilizing the existing
    wireless infrastructure.
  • Design Stage Objective
  • Major Layout Blocks, Better Floorplans

2
Status
  • Structural Verilog complete.
  • Schematics complete except for calc FSM
    (debugging).
  • Layout of basic components complete.
  • Major Layouts
  • Mirror Adder Done
  • Multiplier 90 done
  • SRAM Done (testing)
  • Divider 80 done
  • FPU Prenorm Postnorm 60 done

3
Transistor counts
  • BETTER!!! Total 28,388 transistors
  • Top Three 6,500 trans.
  • 3 x FPU Add/Sub Unit 1500 trans.
  • Control Registers Muxes 2000 trans.
  • Calc 17,950 trans.
  • 2 x FPU Add/Sub Unit 1500 trans.
  • 1 x FPU Mult/Div Unit 5000 trans.
  • 1 x Logshifter 200 trans.
  • 1 x Comparator 800 transistors.
  • FSM Logic 850 transistors
  • 25 x 12-bit M-S En Reg 6600 trans. total
  • 8-1,6-1,4-1,2-1 Mux Sets 3000 trans. total
  • Lookup 3,938 trans.
  • Control Registers Muxes 2000 trans.
  • Control Logic 163 trans.
  • SRAM 6k trans
  • count not including SRAM, with SRAM 36k

4
Top Three Module Floorplan
5
New Mult/Div Layout
6
New Mult/Div Explanation
  • Old Div used simple shift subtract algorithm
    which is applied iteratively, one cycle per bit
  • New Div will use the multiplier to produce
    rolled-out subtractions and shifts. This not
    only makes the design smaller, but also takes
    care of clocking issues ?

7
SRAM Cell Layout
8
SRAM in Layout
9
SRAM Floorplan
10
New Mirror Adder Layout
11
Questions/Concerns
  • Muxing and Routing is our biggest problem, but
    hopefully, the new design of Div/Mult will help
  • Our transistor count is still too high
  • How should we layout 8to1 muxes?
  • Should we move averaging to the output of the
    calc module?
  • Overall floorplan needs to be reconsidered
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