Sin ttulo de diapositiva

1
RICH DAQ ARCHITECTURE
FMEM
PROM
PWR CTRL
DSP
XDR
x2
CLK ADC(2) CS ADC (2) PREamp SEQ(2) RST
PREamp(2) ADC DATA(22)
DMS RD INTx DATA (16) WR A0
GATE ARRAY DATA PROCESSOR
IN-OUT GATE ARRAY
FE SEQ.
LATCH UP PROTECT.
CLOCK
START BUSY
VCC VEE DIGITAL GND ANALOG GND
FMEM
PROM
PWR CTRL
DSP
XDR
x2
CLK ADC (2) CS ADC (2) PREamp SEQ (2) RST PREamp
(2) ADC DATA(22)
DMS RD INTx DATA (16) WR A0
GATE ARRAY DATA PROCESSOR
IN-OUT GATE ARRAY
FE SEQ.
LATCH UP PROTECT.
CLOCK
START BUSY
VCC VEE DIGITAL GND ANALOG GND
6 x 4
DMS MEMORY OVLY. SELECT WR MEMORY WRITE RD MEMORY
READ INTx INTERRUPTION x