Co-design of Custom VLIW-DSP type Data-path Architecture and its Parallel Program based on Formal Verification Technique

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Co-design of Custom VLIW-DSP type Data-path
Architecture and its Parallel Program based on
Formal Verification Technique
K. Seto1, T. Kuroha2, D. Nakatani2, K. Asada2, M.
Fujita2 1Pacific Design Inc, Japan. 2University
of Tokyo, Dept. of Electronics Engineering, Japan.
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Objective

• Design of ASIC(FPGA)Core Processor
• Small sized but performance critical loops are
  executed on VLIW-DSP data-path unit in ASIC(FPGA)
• Exploration of VLIW-DSP data-path architecture in
  ASIC(FPGA) and generation of resulting code for
  given application program

Conclusion

• Exact Phase-coupled Code generation of VLIW-DSP
  solved by symbolic state traversal of formal
  verification
• The minimum-cycle parallel code obtained in
  feasible time for small DFG (20-30 nodes), 5-10
  data-path templates
• Provides platform for architectural exploration
  by changing input data-path templates
  (Retargetable Compilation)

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Our Solution Flow