ALUop 1 X 0 2 X-Y 3 0 Y 4 0 5 X Y

1
RISCEE 3 Architecture
Clock load value into register
ALUop1 X02 X-Y3 0Y4 05 XY
OR gate
2
0 1
ADD1
P0
BZ
AND gate
NOT
PC
Y
Zero
Readaddress Instruction15-0 InstructionMemo
ry
Instruction7-0
ALU3
address WriteData ReadData
Read Data Accumulator WriteD
ata
X
RegWrite
MemWrite
ADD2
3 2 1 0
RegDst
Clock
2
Instruction clear Operation A0
ALUop1 X02 X-Y3 0Y4 05 XY
OR gate
2
0 1
ADD1
0
P0
0
BZ
AND gate
NOT
PC
Y
Zero
Readaddress Instruction15-0 InstructionMemo
ry
Instruction7-0
ALU3
address WriteData ReadData
Read Data Accumulator WriteD
ata
X
RegWrite
1
MemWrite
ADD2
RISCEE 3 Architecture
3 2 1 0
RegDst
0
2
RegDst2 ALU4 MemWrite0 RegWrite1 BZ0 P00
3
Instruction addi data8 Operation A A
data8
ALUop1 X02 X-Y3 0Y4 05 XY
OR gate
2
0 1
ADD1
0
P0
0
BZ
AND gate
NOT
PC
Y
Zero
Readaddress Instruction15-0 InstructionMemo
ry
Instruction7-0
ALU3
address WriteData ReadData
Read Data Accumulator WriteD
ata
X
RegWrite
1
MemWrite
ADD2
RISCEE 3 Architecture
3 2 1 0
RegDst
0
2
RegDst2 ALU5 MemWrite0 RegWrite1 BZ0 P00
4
Instruction add addr8 Operation A A
Memoryaddr8
ALUop1 X02 X-Y3 0Y4 05 XY
OR gate
2
0 1
ADD1
0
P0
0
BZ
AND gate
NOT
PC
Y
Zero
Readaddress Instruction15-0 InstructionMemo
ry
Instruction7-0
ALU3
address WriteData ReadData
Read Data Accumulator WriteD
ata
X
RegWrite
1
MemWrite
ADD2
RISCEE 3 Architecture
3 2 1 0
RegDst
0
0
RegDst0 ALU3 MemWrite0 RegWrite1 BZ0 P00
5
Instruction store addr8 Operation
Memoryaddr8A
ALUop1 X02 X-Y3 0Y4 05 XY
OR gate
2
0 1
ADD1
0
P0
0
BZ
AND gate
NOT
PC
Y
Zero
Readaddress Instruction15-0 InstructionMemo
ry
Instruction7-0
ALU3
address WriteData ReadData
Read Data Accumulator WriteD
ata
X
RegWrite
0
MemWrite
ADD2
RISCEE 3 Architecture
3 2 1 0
RegDst
1
X
RegDstX ALU3 MemWrite1 RegWrite0 BZ0 P00
6
Instruction bne addr8 Operation if (A ! 0)
pcaddr8
ALUop1 X02 X-Y3 0Y4 05 XY
OR gate
2
0 1
ADD1
0
P0
1
BZ
AND gate
NOT
PC
Y
Zero
Readaddress Instruction15-0 InstructionMemo
ry
Instruction7-0
ALU3
address WriteData ReadData
Read Data Accumulator WriteD
ata
X
RegWrite
0
MemWrite
ADD2
RISCEE 3 Architecture
3 2 1 0
RegDst
0
X
RegDstX ALU3 MemWrite1 RegWrite0 BZ0 P00
7
Instruction apc Operation Apc2
ALUop1 X02 X-Y3 0Y4 05 XY
OR gate
2
0 1
ADD1
0
P0
0
X
BZ
AND gate
NOT
PC
Y
Zero
Readaddress Instruction15-0 InstructionMemo
ry
Instruction7-0
ALU3
address WriteData ReadData
Read Data Accumulator WriteD
ata
X
RegWrite
1
MemWrite
ADD2
RISCEE 3 Architecture
3 2 1 0
RegDst
0
3
RegDstX ALUX MemWrite1 RegWrite0 BZ0 P00
8
RISCEE 4 Architecture
Clock load value into register
01 2
P0 (AluZero BZ)
ALUsrcB
PCSrc
012
Y
IorD
ALUOut
MDR2
ALU
Instruction7-0
0 1
2
MemRead
X
PC
IRWrite
1 0
address Read Data Write Data
I R
Read Data
Accumulator WriteData
ALUsrcA
ALUop1 X02 X-Y3 0Y4 05 XY
RegWrite
MemWrite
MDR
1 0
RegDst
Clock
9
T1 all instructions IRMemPC pcpc2
RISCEE 4 Architecture
01 2
P01 BZX
P0 (AluZero BZ)
1
0
ALUsrcB
PCSrc
012
Y
1
IorD
ALUOut
MDR2
ALU
Instruction7-0
1
0 1
2
MemRead
X
PC
IRWrite
1 0
address Read Data Write Data
I R
Read Data
Accumulator WriteData
ALUsrcA
ALUop1 X02 X-Y3 0Y4 05 XY
0
RegWrite
X
MemWrite
MDR
0
1 0
RegDst
X
10
T2 all instructions opcode decode
RISCEE 4 Architecture
01 2
P00 BZ0
P0 (AluZero BZ)
X
X
ALUsrcB
PCSrc
012
Y
X
IorD
ALUOut
MDR2
ALU
Instruction7-0
0
0 1
2
MemRead
X
PC
IRWrite
1 0
address Read Data Write Data
X
I R
Read Data
Accumulator WriteData
ALUsrcA
ALUop1 X02 X-Y3 0Y4 05 XY
X
RegWrite
X
MemWrite
MDR
0
1 0
RegDst
X
11
T3 clear ALUOut0
RISCEE 4 Architecture
01 2
P00 BZ0
P0 (AluZero BZ)
X
X
ALUsrcB
PCSrc
012
Y
X
IorD
ALUOut
MDR2
ALU
Instruction7-0
0
0 1
2
MemRead
X
PC
IRWrite
1 0
address Read Data Write Data
4
I R
Read Data
Accumulator WriteData
ALUsrcA
ALUop1 X02 X-Y3 0Y4 05 XY
X
RegWrite
X
MemWrite
MDR
0
1 0
RegDst
X
12
T4 clear AALUOut
RISCEE 4 Architecture
01 2
P00 BZ0
P0 (AluZero BZ)
X
X
ALUsrcB
PCSrc
012
Y
X
IorD
ALUOut
MDR2
ALU
Instruction7-0
0
0 1
2
MemRead
X
PC
IRWrite
1 0
address Read Data Write Data
4
I R
Read Data
Accumulator WriteData
ALUsrcA
ALUop1 X02 X-Y3 0Y4 05 XY
X
RegWrite
1
MemWrite
MDR
0
1 0
RegDst
0
13
T3 add ALUOutIR7-0
RISCEE 4 Architecture
01 2
P00 BZ0
P0 (AluZero BZ)
X
2
ALUsrcB
PCSrc
012
Y
X
IorD
ALUOut
MDR2
ALU
Instruction7-0
0
0 1
2
MemRead
X
PC
IRWrite
1 0
address Read Data Write Data
3
I R
Read Data
Accumulator WriteData
ALUsrcA
ALUop1 X02 X-Y3 0Y4 05 XY
X
RegWrite
X
MemWrite
MDR
0
1 0
RegDst
X
14
T4 add MDR2MemALUOut
RISCEE 4 Architecture
01 2
P00 BZ0
P0 (AluZero BZ)
X
X
ALUsrcB
PCSrc
012
Y
0
IorD
ALUOut
MDR2
ALU
Instruction7-0
1
0 1
2
MemRead
X
PC
IRWrite
1 0
address Read Data Write Data
X
I R
Read Data
Accumulator WriteData
ALUsrcA
ALUop1 X02 X-Y3 0Y4 05 XY
X
RegWrite
X
MemWrite
MDR
0
1 0
RegDst
X
15
T5 add ALUOut MDR A
RISCEE 4 Architecture
01 2
P00 BZ0
P0 (AluZero BZ)
X
1
ALUsrcB
PCSrc
012
Y
X
IorD
ALUOut
MDR2
ALU
Instruction7-0
0
0 1
2
MemRead
X
PC
IRWrite
1 0
address Read Data Write Data
5
I R
Read Data
Accumulator WriteData
ALUsrcA
ALUop1 X02 X-Y3 0Y4 05 XY
1
RegWrite
X
MemWrite
MDR
0
1 0
RegDst
X
16
T6 add AALUOut
RISCEE 4 Architecture
01 2
P00 BZ0
P0 (AluZero BZ)
X
X
ALUsrcB
PCSrc
012
Y
X
IorD
ALUOut
MDR2
ALU
Instruction7-0
0
0 1
2
MemRead
X
PC
IRWrite
1 0
address Read Data Write Data
4
I R
Read Data
Accumulator WriteData
ALUsrcA
ALUop1 X02 X-Y3 0Y4 05 XY
X
RegWrite
1
MemWrite
MDR
0
1 0
RegDst
0
17
T3 bne if(A!0) PCIR7-0
RISCEE 4 Architecture
01 2
P00 BZ1
P0 (AluZero BZ)
2
X
ALUsrcB
PCSrc
012
Y
X
IorD
ALUOut
MDR2
ALU
Instruction7-0
0
0 1
2
MemRead
X
PC
IRWrite
1 0
address Read Data Write Data
1
I R
Read Data
Accumulator WriteData
ALUsrcA
ALUop1 X02 X-Y3 0Y4 05 XY
1
RegWrite
X
MemWrite
MDR
0
1 0
RegDst
X