ECE 491 Senior Design I

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ECE 491 - Senior Design I

• Lecture 9 - ASM Diagrams
• Fall 2008
• HW?

Prof. John NestorECE DepartmentLafayette
CollegeEaston, Pennsylvania 18042nestorj_at_lafayet
te.edu
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Where we are

• Last Time
• Data Communications The OSI Reference Model
• Asynchronous Serial Data Transmission
• Today
• ASM Diagrams - an alternative state diagram
  notation

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ASM Diagrams

• ASM Algorithmic State Machine
• A flowchart notation for state machines
• Motivation
• High-level description of clock-cycle level
  behavior
• Flowchart to show state flow, output values
• Uses default output values to reduce clutter
• Alternative to traditional state diagrams
• Easier to read for large diagrams
• Prevents inconsistent diagram specifications
• More concise than Verilog code

Christopher R. Clare, Designing Logic Using
State Machines, McGraw-Hill, 1973
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Flavors of ASM Diagrams

• Low-level
• Cycle-by-cycle timing
• Detailed specification of input / output values
• Equivalent to standard state diagram
• Register-Transfer Level
• Cycle-by-cycle timing
• Abstract operations (can map directly to low
  level)

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ASM Elements
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Describing an ASM State
Note all other outputs are 0!
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State Description w/ Complex Branches
State Diagram Equivalent (Fill In)
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ASM Diagram Pitfall

• Conditional output boxes specify values
• Conditional output boxes dont specify sequence

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ASM Example - Single Pulser

• Problem Statement Given an active-high,
  debounced, pushbutton, devise a circuit to sense
  when the button is pressed and assert an output
  signal for one clock pulse. The system should
  not allow for additional assertions until after
  the button is released.

Source F. Prosser and D. Winkel, The Art of
Digital Design, Prentice-Hall, 1987
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ASM Example Single Pulser
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ASM Example - System Clock

• Problem Statement
• Design a hazard-free system clock that runs in
  two modes, automatic and manual. The auttomatic
  mode is a fixed-frequency mode derived from a
  continuously running clock or oscillator. The
  manual mode should produce a true clcok ouput
  when a button is pressed, and a false output
  otherwise.
• Activating the mode switch must never cause
  truncation of a clock cycle.
• In the automatic mode, the clock circuit should
  ignore the pushbutton.

Source F. Prosser and D. Winkel, The Art of
Digital Design, Prentice-Hall, 1987
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ASM Example System Clock
MAN
Up
Manual
CLK
Down
PB
Auto
OSC
Down
Manual
Auto
Up
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Example MIPS Multicycle Control Unit
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Example MIPS Multicycle Design
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Multicycle Control - ASM Diagram Part 1
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Multicycle Control -ASM Diagram Part 2
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Multicycle Control -ASM Diagram Part 3
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3
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RTEX
BR
ALUSrcA 1 ALUSrcB 00 ALUOp 10
ALUSrcA 1 ALUSrcB 00 ALUOp
01 PCWriteCond PCSource 01
RTWB
RegDst 1 RegWrite MemtoReg 0
0
0
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Register-Transfer Level ASM Diagrams

• Key idea
• Use same notation as regular ASM
• Instead of outputs, write register transfers
• Advantages
• Plan complex designs before details are nailed
  down
• Estimate resource costs by counting operations in
  each state

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Multicycle Control - ASM Diagram Part 1
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Multicycle Control -ASM Diagram Part 2
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Multicycle Control -ASM Diagram Part 3
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Coding ASM Diagrams in Verilog

• Use same basic pattern as normal FSMs
• Clocked always block for registers
• Combinational always block for next state /
  output logic
• Key difference explicit default

always _at_ begin out1 0 out2 0
case (cs) S0 begin out1
1 if (in1) out2 1 ns
S1 end . . . endcase
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Example MIPS Control Unit - Part 1

• module mips_control( clk, reset, Op, PCWrite,
  PCWriteCond, IorD, MemRead,
• MemWrite, MemtoReg, IRWrite,
  PCSource, ALUOp
• ALUSrcB, ALUSrcA, RegWrite,
  RegDst )
• input clk
• input reset
• input 50 Op
• output PCWrite
• output PCWriteCond
• output IorD
• output MemRead
• output MemWrite
• output MemtoReg
• output IRWrite
• output 10 PCSource
• output 10 ALUOp
• output ALUSrcA
• output 10 ALUSrcB
• output RegWrite
• output RegDst

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Example MIPS Control Unit - Part 2

• reg PCWrite
• reg PCWriteCond
• reg IorD
• reg MemRead
• reg MemWrite
• reg MemtoReg
• reg IRWrite
• reg 10 PCSource
• reg 10 ALUOp
• reg ALUSrcA
• reg 10 ALUSrcB
• reg RegWrite
• reg RegDst
• parameter R_FORMAT 6'd0
• parameter LW 6'd35
• parameter SW 6'd43
• parameter BEQ 6'd4
• parameter J 6d2

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Example MIPS Control Unit - Part 3

• reg 30 current_state, next_state
• always _at_(negedge clk)
• begin
• if (reset) current_state lt S0
• else current_state lt next_state
• end
• always _at_(current_state or Op)
• begin
• // default values
• PCWrite 1'b0
• PCWriteCond 1'b0
• IorD 1'bx
• MemRead 1'b0
• MemWrite 1'b0
• MemtoReg 1'bx
• IRWrite 1'b0
• PCSource 2'bxx

• RegWrite 1'b0
• RegDst 1'bx
• case (current_state)
• S0 begin
• MemRead 1'b1
• ALUSrcA 1'b0
• IorD 1'b0
• IRWrite 1'b1
• ALUSrcB 2'b01
• ALUOp 2'b00
• PCWrite 1'b1
• PCSource 2'b00
• next_state S1
• end
• endcase
• end

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Homework Assignment

• 7-Segment Display Control circuit (Lab 2)
• Draw an ASM Diagram of a 7-segment display
  controller that uses a state machine
• Re-use your design from Lab 2 if its a state
  machine. Otherwise, create a new FSM-based
  design.
• Hand in on Monday, Oct. 1

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Coming Up

• More about Data Communications
• Asynchronous Serial Receiver
• Transmission Codes
• Synchronization Issues with Multiple FSMs