Efficient Automatic Resolution of Encoding Conflicts Using STG Unfoldings

1
Efficient Automatic Resolution of Encoding
Conflicts Using STG Unfoldings

• Victor Khomenko
• School of Computing Science,
• Newcastle University, UK

2
Asynchronous circuits

• The traditional synchronous (clocked) designs
• lack flexibility to cope with contemporary
• design technology challenges
• Asynchronous circuits no clocks
• Low power consumption and EMI
• Tolerant of voltage, temperature and
• manufacturing process variations
• Modularity no problems with the clock skew
• and related subtle issues
• ITRS05 22 of designs will be driven by
  handshake clocking in 2013, and 40 in 2020
• Hard to synthesize efficient circuits
• The theory is not sufficiently developed
• Limited tool support

3
Motivation

• Resolution of encoding conflicts is one of the
  most difficult tasks in logic synthesis
• The quality of the resulting circuit (in terms of
  area and latency) depends to a large extent on
  the way the encoding conflicts were resolved

4
Example VME Bus Controller
5
Example Encoding Conflict
6
State Graphs vs. Unfoldings

• State Graphs
• Relatively easy theory
• Many efficient algorithms
• Not visual
• State space explosion problem

7
State Graphs vs. Unfoldings

• Unfoldings
• Alleviate the state space explosion problem
• More visual than state graphs
• Proven efficient for model checking
• Quite complicated theory
• Not sufficiently investigated
• Relatively few algorithms

8
Example Encoding Conflict
e10
e8
dtack-
dsr
e1
e2
e3
e4
e5
e6
e7
e12
lds
ldtack
dtack
dsr
lds
d-
dsr-
d
Code(conf)10110
Code(conf)10110
lds-
ldtack-
e9
e11
9
Example Resolving the conflict
10
Example Resolving the conflict
dtack-
dsr
csc
001000
000000
100000
100001
lds
ldtack-
ldtack-
ldtack-
dtack-
dsr
011000
100101
010000
110000
ldtack
lds-
lds-
lds-
dtack-
dsr
110101
011100
110100
010100
d
d-
dtack
dsr-
csc-
011111
111111
110111
011110
11
Example Resulting Circuit
Data Transceiver
Device
Bus
d
lds
dtack
dsr
csc
ldtack
12
Core map

• Cores often overlap
• High-density areas are good candidates for signal
  insertion
• Analogy with topographic maps

13
Transformations

• Need to check the validity of the transformation
  safeness, bisimulation, not delaying inputs,
  preserving semi-modularity
• The validity should be checked before the
  transformation is performed, i.e. on the original
  prefix (to avoid backtracking)
• Perform the transformation directly on the prefix
  to avoid re-unfolding
• Re-unfolding is time-consuming
• Good for visualization (re-unfolding can
  dramatically change the look of the prefix)
• Can transfer unresolved encoding conflicts
  between the iterations of the algorithm

14
Sequential pre-insertion

• Preserves safeness
• Preserves traces
• Can introduce deadlocks check that the new
  transition never steals tokens from any other
  enabled transition
• state property can be checked on the prefix
• Easy to check that inputs are not delayed
• Can violate semi-modularity
• state property can be checked on the prefix

15
Sequential post-insertion

• Preserves safeness
• Yields a bisimular PN
• Preserves semi-modularity
• Easy to check (conservatively) that inputs are
  not delayed

16
Concurrent insertion

• Can introduce non-safeness and/or deadlocks
• the correctness can be checked on the prefix
• Easy to check that inputs are not delayed
• Preserves semi-modularity

17
Equivalent insertions

• Equivalence is easy to check
• Fewer transformations to consider
• Can convert to canonical form, e.g.
  pre-insertions
• No need to check validity post-insertions are
  always valid

18
Commutative insertions

• Two transition insertions commute if they can be
  performed in any order
• concurrent insertions commute with any other
  insertions
• pre-insertions commute with post-insertions
• two pre/post-insertions commute iff they split
  different transitions or the sets of split off
  places do not overlap
• A valid insertion remains valid if another valid
  commutative insertion is applied first, i.e. the
  validity needs to be checked only once

19
Outline of the algorithm

• Compute unfolding prefix of the STG
• Compute conflict cores and terminate if none
• Compute the set of valid transition insertions
• Find a subset of these insertions such that
• no two of them are
• non-commuting, or
• concurrent, or
• in auto-conflict, or
• one of them can trigger the other
• consistent assignment of signs is possible
• some encoding conflicts are resolved
• a cost function is minimised
• Apply the insertions to the STG and the prefix
  and goto 2

20
Cost function

• Parameterised by the user takes into account
• the number of unresolved CSC and USC cores
• the delay introduced by the insertion
• the number of syntactic triggers of all non-input
  signals
• the number of inserted transitions of a signal
• the number of signals which are not locked with
  the newly inserted signal

21
Case study 1 VME bus controller
e10
e8
dtack-
dsr
e1
e2
e3
e4
e5
e6
e7
e12
lds
d-
ldtack
dsr-
dtack
d
dsr
lds
lds-
ldtack-
e9
e11

• Fully sequential solution
• Fully concurrent solution
• Solution with two set and two reset transitions
• Explored design space 17 different solutions

22
Case study 2 8-way sequencer

• Fully concurrent solution with 3 signals (csc1 is
  set and reset twice)
• Petrify needs 4 signals

23
Experimental results

• Compared with Petrify and the ILP approach of
  CC06
• Small benchmarks
• always better in terms of inserted signals
• 8.5-8.8 smaller area
• Jordi Cortadella was impressed
• Scalable benchmarks (the tool of CC06 was not
  available)
• almost the same area and number of signals
• runtime and memory consumption are better by
  orders of magnitude
• some intractable for Petrify benchmarks were
  easily solved

24

• Thank you!
• Any questions?