Resolution of Encoding Conflicts by Signal Insertion and Concurrency Reduction based on STG Unfoldin

1
Resolution of Encoding Conflicts by Signal
Insertion and Concurrency Reduction based on STG
Unfoldings

• V. Khomenko, A. Madalinski and A. Yakovlev
• University of Newcastle upon Tyne

2
Signal Transition Graph (STG)
Data Transceiver
Device
Bus
d
lds
dsr
VME Bus Controller
dsw
ldtack
dtack
3
Encoding conflicts

• pairs of semantically different states with the
  same binary encoding
• not distinguishable at the circuit level
• encoding conflicts have to be resolved before we
  can proceed with synthesis
• Transformations
• signal insertion introduces additional internal
  signal (memory) helping to trace the current
  state
• concurrency reduction introduces additional
  ordering constraints making some of the
  conflicting states unreachable
• both are needed to explore a larger design space!

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Example CSC conflict
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CSC resolution signal insertion
dtack-
dsr
csc
010000
000000
100000
100001
lds
ldtack-
ldtack-
ldtack-
dtack-
dsr
010100
101001
000100
100100
ldtack
lds-
lds-
lds-
dtack-
dsr
101101
011100
101100
001100
d
d-
dtack
dsr-
csc-
011111
111111
101111
011110
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CSC resolution concurrency reduction
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Framework for visualisation interactive
resolution of encoding conflicts

• manual vs. automatic resolution of coding
  conflicts
• automatic ? can produce sub-optimal solutions
• manual ? crucial for finding good (low-latency,
  compact elegant) synthesis solutions
• interactivity is good!

• visualisation concepts
• emphasise essential information
• avoid information overload

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STG unfolding

• partial order model
• infinite acyclic net, simple structure
• finite complete prefix
• finite initial part of unfolding
• contains all the reachable states
• alleviates state space explosion problem
• more visual then state graphs
• proven efficient for model checking

9
State Graphs vs. Unfoldings
M
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Visualisation of conflicts Height map

• cores often overlap
• high-density areas are good candidates for signal
  insertion
• analogy with topographic maps

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Height map an example
Core map
Height map
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Resolution of encoding conflicts

• Signal insertion
• insert t in a core
• t- must be added outside the core preserving
  consistency
• inserted transitions must not trigger an input
  signal

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Concurrency reduction

• addition of causal constraint, i.e. a new place

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Resolution of encoding conflicts

• Forward concurrency reduction
• bringing forward the ending point of concurrency
• dragging f into the core

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Resolution of encoding conflicts

• Backward concurrency reduction
• delaying starting point of concurrency
• dragging f into the core

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Resolution of encoding conflicts
Concurrency reduction an example
backward
forward
backward
inputs b,c,f outputs a,d,e
inputs a,b outputs c,d,e
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Overview of the resolution process
phase 2
concurrency reduction
signal insertion
phase 1
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Cost function

• cost a1?? a2?logic a3?core
• ?? estimated delay caused by transformation
• ?logic estimated increase in complexity of logic
  
• ?core number of eliminated cores,
• ai parameters chosen by the designer
• Calculated on the original unfolding prefix

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Validity

• signal insertion well-developed, e.g. weak
  bisimulation
• concurrency reduction more challenging, e.g.
• not even language-equivalent
• events can become dead
• introduction/disappearance of deadlocks

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Validity aspects

• I/O interface preservation
• the interface between circuit and its
  environment should be preserved
• conformation
• no wrong behaviour should be introduced
• liveness
• no interesting behaviour should be completely
  eliminated
• technical restrictions
• boundedness, speed-independence, etc.

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Validity notion

• natural to use partial order framework when
  speaking about concurrency reduction!
• plan
• define a valid realisation relation on partial
  order analog of traces (processes)
• define valid realisation relation on systems

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Validity notion processes

• can easily eliminate silent actions (e.g.
  internal signals) preserving causality
  abstraction

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Validity notion processes

• step 1 increasing concurrency of inputs
• step 2 decreasing concurrency of outputs

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Validity notion processes

• step 1 increasing concurrency of inputs

• step 2 decreasing concurrency of outputs

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Validity notion processes
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Validity notion systems

• valid realisation

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Validity notion systems
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Case study AD converter controller
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Conclusions

• combined framework for resolution of encoding
  conflicts based on cores in the STG unfolding
• larger design space exploit the area/delay
  trade-off
• novel validity condition
• Future work
• more automation
• improving cost function
• performing transformation directly on the
  unfolding prefix rather than the STG