The Trigger Prototype Board Status

1
The Trigger Prototype Board Status
On behalf of trigger group D. Nicolò F.
Morsani S. Galeotti M. Grassi
Marco Grassi INFN - Pisa
2
Hardware board Type 1

• VME 6U
• A-to-D Conversion
• FADC with differential inputs bandwidth limited
• Trigger
• LXe calorimeter
• timing counters
• No use for the tracking chambers
• I/O
• 16 PMT signals
• 2 LVDS transmitters
• 4 in control signals

16 x 10
Control FPGA
Type 2 boards
3
Hardware board Type 2
Type 1

• VME 9U
• Matched with the Type 1 boards
• I/O
• 10 LVDS receivers
• 2 LVDS transmitters
• 4 in control signals
• 3 out signals

10 x 48
Control FPGA
Trigger Sync Start
to next Type 2
4
Hardware system structure
2 boards
LXe inner face (312 PMT)
LXe lateral faces (208 PMT) (120x2 PMT) (40x2 PMT)
1 board
1 board
2 x 48
2 or 1 boards
Timing counters (160 PMT) or (80 PMT)
2 VME 6U 1 VME 9U
5
Present status

• Prototype board Type0
• Modified Type1
• Check of the connectivity with the Type2
• Study the FADC coupling
• Verify the chosen algorithms
• Selected components (all delivered)
• Main FPGA XCV812E-8-FG900 and XCV18V04 config.
  ROM
• Interface and control CPLD XC95288XL-FG256
• ADC AD9218 (dual 10 bits 100 MHz)
• Clock distribution CY7B993V (DLL multi-phase
  clock buffer)
• LVDS serializer DS90CR483 / 484 (48 bits - 100
  MHz - 5.1 Gbits/s)
• LVDS connectors 3M Mini-D-Ribbon
• Analog input by 3M coaxial connectors
• Control and debug signals in LVDS standard
• FPGA design completed
• FPGA design and simulation completed (runs at 100
  MHz)
• VHDL parameterization is ready

6
Prototype board Type 0

• VME 6U
• A-to-D Conversion
• Trigger
• I/O
• 16 PMT signals
• 2 LVDS transmitters
• 4 in/2 out control signals
• Complete system test

16 x 10
Analog receivers
Control CPLD
Sync Trigger Start
Spare in/out
VME
7
The Analog input stage
AD8138

• BW limitation
• Unipolar or bipolar inputs
• Variable gain
• Pedestal adjust

8

• Board Design ? completed
• Implementation by means of CADENCE
• Schematic simulation completed
• Components footprints checked
• Board routing ? ready
• 10 layers
• 4 GND Power
• 6 signals
• DC/DC converters
• A32 mode
• Block transfer
• Board production
• PCB producer contacted ready for a production
  offer
• Delivery end of July
• Test September

9
DRS Chip

• Prototype received Nov. 02
• Tests Dec. 02 April 03
• Digital part works perfectly
• Analog parts requires redesign
• DLL and VME board built by Siena

10
Test results
fsampGHz vs. VddV
fsampGHz vs. VcontrolV
fsampGHz vs. Tdeg. C
11
Running Domino Wave
Denable
Dtap
Jitter after 32 turns 1ns
32 Domino cycles _at_ 320ns
Readout Shift Register
SR_CLK SR_RESET SRIN SROUT
768
12
DLL Design
R. Paoletti, N. Turini, INFN

• DLL works with jitter of 200 ps RMS
• Siena (N. Turini, R. Paoletti, MAGIC) designs VME
  board

13
DRS Readout
Input pulse
Digitized output pulse
5ns risetime
8ns risetime
14
Problems in analog part
source
Capacitances Gate-Bulk 10.6 fF Source-Bulk
13.5 fF Drain-Bulk 2.4 fF
gate
drain
PHI
Csamp
PHI
Bus
Bus capacitance too high (110pF)
15
DRS Redesign

• Reduce bus-bulk capacitance by 6x
• Reduce bus-bus capacitance
• Use current-mode readout

R
I
Vin
Vout
read
write
. . .
G. Varner, Univ. of Hawaii STRAW2 chip
C
16
Plans

• UMC 0.25mm technology
• Next Submission Oct. 20th
• Production time 9 weeks
• VME board design in parallel (Siena)
• Rectangle 5 x 5 mm2
• Reduce minimum sampling speed to 500 MHz (for DC)
• Daisy chain mode for N x 1024 bins
• Dual-channel for deadtimeless operation
• 4 chn. Q mode 4 chn. I mode
• Production run spring 2004

17
DRS options
Input
Input
Readout
Domino Wave
Dual-channel mode
Daisy-chain mode
18
DRS (DAQ)
2002
2003
2004
2005
Tests
1st Prototype
2nd Prototype
Boards Chip
Test
Test
Milestone
Assembly
Design
Manufactoring
19
DAQ System
area
800 160
7m
to trigger (20m)
Trigger
PMT
Active Splitter
monitor
10 VME crates
2m
optical fiber (20m)
DRS Board (16chn)
Front-End PCs
Rack PC (Linux)
SIS 3100
Rack PC (Linux)
Rack PC (Linux)
1920
7m
Rack PC (Linux)
DRS Board (16chn)
DC
Pre-Amp
Rack PC (Linux)
Gigabit Ethernet
Rack PC (Linux)
Rack PC (Linux)
Rack PC (Linux)
Raw data 2880 channels 100 Hz 50 / 10 / 10
occupancy 2kB / waveform -gt 5 x 25 MB/sec.
Rack PC (Linux)
Rack PC (Linux)
Fitted data 10 Hz waveform data -gt 1.2
MB/sec 90 Hz ADC / TDC data -gt 0.9 MB/sec
Rack PC (Linux)
On-line farm
storage
20
Waveform analysis
Original Waveform

• Zero suppression in FPGA
• Single hit
• ADC/TDC derived in FPGA
• Multiple hit
• Waveform compressed in FPGA (2x12 bit -gt 3 Byte)
• Waveform fitted / compressed in PC cluster
• Store ADC/TDC only for calibration events
• Store (lossless) compressed waveforms for MEG
  candidates

Region for pedestal evaluation
T
integration area
Difference Of Samples
Threshold in DOS
ADC2/TDC2
ADC1/TDC1
21
ROOT for online analysis

• ROOT becomes more stable and is now widely used
• Online extensions are underway (life display of
  histos and N-tuples)
• Propose to use ROOT for online monitoring and
  single event display, CARROT for Web display
• For offline analysis, keep possibility to use
  ROOT or PAW

ROOT GUI
offline analysis ROOT
.root
ROOT
Analyzer
FE
offline analysis HBOOK
.rz
PAW
.mid
online offline