A Design Environment for High Throughput, Low Power Dedicated Signal Processing Systems

1
A Design Environment for High Throughput, Low
Power Dedicated Signal Processing Systems

• Rhett Davis, Prof. Robert W. Brodersen BWRC
  Summer 2001 Retreat

2
Direct Mapping for Wireless Algorithms

• Low processing rates (wireless baseband 25
  Msps)
• High Complexity
• Low Power

P ? f ? C ? VDD2
Use low VDD / parallelism
3
Capturing Design Decisions

• Categories
• Function - basic input-output behavior
• Signal - physical signals and types
• Circuit - transistors
• Floorplan - physical positions

How to get layout and performance estimates in a
day?
4
Chip-in-a-Day Design FlowA User Perspective

• Allow regeneration and reanalysis of the design
  for small changes at the push of a button
• Uses flow dependency graphs to manage large
  projects

5
Simplified View of the Flow

• New Software
• Generation of netlists from Simulink
• Merging of floorplan from last iteration
• Automatic routing and performance analysis
• Automation of flow as a dependency graph (UNIX
  MAKE program)

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Progress Since January Retreat

• Completed Design Flow Integration
• Hierarchical PR
• Clock Tree Synthesis
• Custom Synthesizer
• Gated Clocks
• Verification
• Sim Only types in Simulink
• Black Box Macros
• Pad Rings
• Pre-Routes

• In Progress
• CTGEN Integration
• Support for Physical Compiler Mustang
• 2 Chips Near Completion
• Soft-Output Viterbi Chip
• TCI Baseband Chip
• Planned
• Genesis/Integration Ensemble Integration
• Timing Driven PR Integration

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TDMA Baseband Receiver

• 500k transistors
• 0.18 mm
• 1.0 V
• 25 MHz
• 1.1 mm2
• 21 mW
• single phase clock
• 5 clock domains
• 2 layers of PR hierarchy

carrierdetection
frequency estimation
rotate correlate
control
8
Elaboration Steps
The BCC program translates the Simulink design
into an electronic design format
The EDIF file is imported into Cadence DFII as
raw views
The leaf-cells of the raw hierarchy (called
macros) are elaborated the Module Compiler code
is synthesized to a standard-cell netlist
The elaborated hierarchies for each macro are
stitched together with the top-level raw
hierarchy into a single hierarchical netlist
Because no clock net exists in Simulink, one must
be inferred from the Enable ports
The logical hierarchy is selectively flattened
and global nets are expanded to generate the view
from which physical design can begin
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Floorplanning Routing Steps
10
Verification Steps
EPIC Simulations are launched on the ctphysical
hierarchy using vectors dumped from Simulink,
keeping track of logic errors and power
dissipation
Calibre DRC and LVS checks are performed on the
layout
Parasitic extractions are performed and stored as
HSPICE netlists
An RC-extraction of the clock-tree is performed
and simulated with Spectre to determine clock
skew and power
The same EPIC simulation as before can be run on
the extracted netlists