Power Efficient Rapid Hardware Development using CoDeL and Automated Clock Gating

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Power Efficient Rapid Hardware Development using
CoDeL and Automated Clock Gating

• Nainesh Agarwal Nikitas Dimopoulos
• University of Victoria, Canada
• ISCAS, May 24, 2006

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Outline

• Motivation
• Clock Gating
• System Level Design Languages
• CoDeL
• Power Savings Estimation Framework
• Evaluation 2D DWT
• Conclusion

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Motivation

• As DSP processing algorithms become complex,
  power requirements increase
• Low battery life
• Expensive cooling and packaging techniques, which
  may increase the size of the device
• Lower circuit density
• Shorter component life
• Long design cycles for hardware architectures
• Up to a year for a team of engineers to develop
  an ASIC!
• Emergence of System-Design Languages (SLDLs)
• Do not address power dissipation
• Power efficient architecture design is tricky by
  hand and requires even longer lead times.

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Clock Gating

• Reduce dynamic power dissipation
• Reduce the clock switching activity
• Enable clock only when a useful write is needed

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System Level Design Languages

• Started late 1990s
• Provide a high level of abstraction for system
  development

• Categories
• Extend existing HDLs SystemVerilog
• Extend existing software languages SystemC,
  SpecC, Handel-C, JHDL
• Newly created languages Rosetta, CoDeL
• Algorithmic level design
• Only CoDeL and Handel-C

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CoDeL - Overview

• CoDeL (Controller Description Language), targets
  the specification and design at the behavioral
  level.
• Order of the statements implicitly represents the
  sequence of activities.
• Extracts the data and control flow from the
  program automatically, assigns the necessary
  hardware blocks and exploits inherent
  parallelism.
• Similar to the C language, so easy to learn.
• Includes a library of I/O protocols that simplify
  (sub)system interaction.
• Compiler produces synthesizable VHDL code which
  can be targeted to any technology including FPGA
  or ASIC.

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CoDeL Clock Gating

• Example shows write in state x
• Gate turned on in state x-1, off in state x1

State x - 1
State x
State x 1
Clk
Enable
GClk
Data Latched
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Example (Counter)
module counter ( in inc, out
countOut8 ) register count8 if (inc
1) count count 1
countOut count
count gated on
countOut gated on
Counter
inc
countOut
Reset
Clk
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Power Savings Estimation Framework

• Power saved
• Power saved in avoiding useless switching
• Power saved in avoiding clock switching
• Power required for clock gating (overhead)

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Implementation (2D DWT)
Analysis Filter Bank Module
fStart
Start
Start
fReady
Ready
Ready
Register File
StartPt
StartPt
EndPt
EndPt
M (Rows)
Step
Step
N (Cols)
Size (MN)
Start
iStart
Ready
iReady
StartPt
Forward/Inverse
EndPt
Step
DWT Module
Synthesis Filter Bank Module
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Implementation (Contd.)

• DWT, Analysis and synthesis filter bank modules
• 120 lines of CoDeL code each
• Generate about 1000 lines of VHDL code each
• Synthesized using Synopsys and TSMC 0.18-micron
  CMOS technology
• 10 MHz clock used for synthesis and simulation

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Power Savings (statistical)

• Synopsys Power Analysis
• Default static probabilities on switching activity

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Power Savings (statistical)
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Power Savings (Simulation)

• Synopsys Power Analysis
• Switching activity annotated using simulation
  (Image Lena)

80
80
60
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Power Savings Estimation
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Conclusion

• First power aware algorithmic level design
  platform
• Automated clock gating effective at reducing
  dynamic power dissipation
• Power savings estimation fast and provides decent
  guidelines
• Future research
• Efficient clock gating
• State minimization and register reuse in CoDeL
• Automated pipelining
• Automated power gating
• Better estimation accuracy
• Benchmark circuits

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Questions
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(No Transcript)
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Synopsys vs. CoDeL Clock Gating
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Synopsys vs. CoDeL Clock Gating