Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating

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Ultra Low-Power Clocking Scheme Using Energy
Recovery and Clock Gating

• ELEC 5705
• Harry Tai

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Introduction

• What is the major obstacle to the realization of
  high-performance VLSI system-on-chip design?
• Power consumption
• Increase complexity of synchronous SoC systems
• Increase complexity of the clock network and
  clock power
• For example, Xeon Dual-core processor.

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• What can we do?
• Decreasing the power consumption of the clock
  networks.
• Energy recovery and clock gating are techniques
  developed for low power digital circuits.
• In this experiment, they are using TSMC 0.25 µm
  technology.

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Background

• Energy recovery signal has a slow falling/rising
  transition. (only 1/2Vdd)
• Energy recovery technique is to reduce the power
  consumption on the capacitive signal.
• We can enhance its performances
• Use Sinusoidal signal
• use the energy recovery clocked flip-flop
• Clock gating

Cg
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Energy Recovery Clocked Flip-Flop

• Conventional Four-phase transmission gate, FPTG
• It has a huge delay, because it needs for four
  sinusoidal signals
• Sense Amplifier energy recovery FF, SAER
• Its fast and fairly low-power at high data
  activity, but it has substantiate power
  consumption at low data activity
• Static differential energy recovery FF, SDER
• Low power consumption at low data activity
• Differential conditional-capturing energy
  recovery, DCCER
• Does not contribute to the charge sharing, low
  power consumption at low data activity
• Single-ended conditional-capturing energy
  recovery, SCCER
• Reduces the charge sharing, low power consumption
  at low data activity

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DCCER and SCCER
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• Delay versus frequency for all flip-flops

• Power versus data switching activity at 200 MHz

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Energy Recovery Clocking

• The clock was disturbed using an H-tree network
  on metal-5 layer, which has the smallest
  parasitic capacitance to the substrate.
• The width of the clock tree interconnects was
  selected to be the maximum.
• Can minimize parasitic resistances
• Can also minimize clock skew

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Resonant energy recovery clock generator
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Typical waveform of generated energy
recovering-clock signal
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Power consumption on all Flip-Flops
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Summary of Energy Recovery Clocking

• Energy recovery technique is mainly working on
  the clock networks and input gate capacitances.
• Because of the slow falling/rising transition of
  energy recovery signals, applying energy recovery
  techniques to internal nodes could cause the
  short-circuit power.
• This technique can reduce the power due to clock
  distribution by more than 90 compare to
  square-wave clocking.

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Clock Gating

• The energy recovery clocked FF cannot save power
  during sleep mode if the clock is still running.
• To achieve this goal, we can replace the inverter
  gate with a NOR gate.
• When enable is on, NOR gate will disable the
  clock signal in the idle state.
• When enable is off, NOR gate is just acting as a
  NOT gate.

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Clock gate for SCCER
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Summary of Clock Gating

• This is not only turn off the pull down path, but
  also prevents any evaluation of the data.
  Furthermore, the internal clock is stopped and
  the switching is prevented as well.
• Power savings of more than 1000 times are
  obtained during the idle state when compared to
  the power consumed without clock gate.

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Test and Measurement Result

• To demonstrate the feasibility and effectiveness
  of the proposes energy recovery clocking scheme
  and flip-flops, a pipelined array multiplier has
  been designed using the proposed clocking scheme.
  
• The multiplier is a 64 x 64-bit array multiplier,
  pipelined in 8 stages with the SCCER flip-flops
  as pipeline flip-flops.

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Measured Sinusoidal energy recovery clock signal
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The power saving on flip-flops varies between 68
and 39 depending on the data switching activity.
0 Data activity
50 Data activity
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Conclusion and Future Work

• In simulation, the results show a power reduction
  of 90 on the clock-tree and total power savings
  of up to 83 as compared to the square-wave
  clocking.
• In fabricated, the results show a power reduction
  of 70 on the clock-tree and total power savings
  of 25-69 as compared to the square-wave
  clocking.
• Further reduces the internal node energy in the
  flip-flop