Combinational%20Logic%20Design

1
Combinational Logic Design

• Combinational Circuits
• Design Topics
• Analysis Procedure
• Design Procedure
• Common Building Blocks
• Hardware Design Languages

Read MK 87-124, 141-161, 201-229
2
4 Bit ALU Design Elements
Negate
4 Bit Adder
Negate
Negate
4 Bit Adder
4 Bit Adder
Quad 41 Multiplexor
3
Combinational Circuits

• In combinational circuits, there is no way for a
  signal to flow from a gate output to one of its
  inputs.
• so, outputs depend only on current input values
  (not past)

• non-combinational circuits use feedback to
  implement storage
• Combinational circuits are essential building
  blocks.
• Each output of a combinational circuit is a
  function of the input values.
• each output can be specified by a truth table or
  Boolean exp.
• analysis circuit ? specification
• synthesis specification ? circuit

4
Hierarchical Design

• Complex systems are designed by assembling
  simpler parts in a systematic and (usually)
  hierarchical way.
• complex function at top of hierarchy, simple
  gates at bottom
• design process can be top-down or bottom-up
• Key concept is composition of simpler circuit
  blocks to produce more complex blocks.

odd(X0,X1,X2) odd(X0,odd(X1,X2))
Z0odd(X0,,X8)
odd(X0,X1) nand(nand(X0,nand(X0,X1)),
nand(X1,nand(X0,X1)))
odd(X0,,X8)odd(odd(X0,X1,X2),
odd(X3,X4,X5),odd(X6,X7,X8))
5
Design Concepts

• Hierarchical design is essential for managing
  complexity allows us to understand larger
  circuits.
• Design re-use is a key tool for reducing design
  effort.
• apply common building blocks (functional blocks)
  to construct larger systems
• large designs may contain many instances of a
  given block
• generic design elements implement common
  functions but may differ based on parameter
  values
• e.g. an odd function block, with number of inputs
  as a parameter
• Top-down design, goes from high level
  specification to simpler components using
  iterative refinement.
• In bottom-up design, we identify construct
  common elements that can be re-used multiple
  times.

6
Analyzing Combinational Circuits

• Purpose of analysis is to determine what a
  circuit does.
• Procedure
• 1. verify that circuit is combinational
• 2. label all inputs, outputs and internal nets
• 3. write logic equations for internal nets in
  terms of inputs
• 4. write logic equations for outputs in terms of
  inputs
• and simplify

T2A?B
T1B ?C
T3AT1AB ?C
T4T2?DA?B ?D
F1T3T4 AB ?CB ?D BD ?
F2T2DA?BD
7
Derivation of Truth Tables

• Can derive truth tables directly from circuit.
• Procedure
• 1. For n input circuit, truth table has 2n rows,
  one for each binary number from 0 to 2n-1.
• 2. Label internal nets and place columns in truth
  table for internal nets and outputs.
• 3. Fill in columns for internal nets and outputs.

8
Designing Combinational Circuits

• Procedure
• 1. Determine number of inputs and outputs and
  assign a symbol to each.
• 2. Derive truth table for each output.
• 3. Obtain Boolean expressions for each output.
• 4. Create an appropriate logic diagram.
• 5. Verify correctness by analysis and/or
  simulation.
• Example design circuit with 3 inputs, 1 output
  the output should be 1 when the binary value of
  the inputs is lt3.

F X ?Y ?X ?Z ?
9
BCD to Excess 3 Code Converter

• Excess-3 code for a decimal digit is the binary
  value for the decimal number plus 3.

10
Decoders

• A binary-to-unary decoder converts a binary input
  value with n bits to one of 2n possible output
  values.

11
Decoder Schematic Simulation
12
Encoders

• A unary-to-binary encoder converts one of 2n
  input values to an encoded binary value.

A1D2D3 A0D1D3

• A priority encoder converts the first of 2n input
  values that are 1 to the corresponding encoded
  binary value.

A1D3D2A0D 3D2?D1V D3D2D1D0 -- valid
output
13
Multiplexers

• A multiplexer (a.k.a. data selector) has n
  control inputs, 2n data inputs a single data
  output
• control input value connects one data input to
  output
• circuit similar to decoder
• optional enable input allows construction of
  larger muxes
• implement with AND at output
• alternative implementation uses transmission gates

14
Demultiplexers

• A demultiplexer has n control inputs, 2n data
  outputs a single data input
• control input value connects data input to one of
  the outputs

• Mux demux can be used to transmit several low
  speed signals on a single wire.

15
Choosing the Best Circuit

• Often there are many alternative circuits we can
  use.
• trade-off between circuit cost and performance
• The complexity of a circuit is the number of
  elementary components needed to implement it.
• often, we count simple gates (or gate
  equivalents)
• example
• 8 bit decoder on page 3.10 requires 19 simple
  gates
• an n bit decoder using the same design requires
  n(log2n -1) log2n simple gates
• The worst-case delay of a circuit is the maximum
  time required for an input signal change to
  affect an output.
• estimate by looking for longest input-to-output
  path (most simple gates) and counting one unit
  per gate in path
• can estimate more precisely if gate delays are
  given

16
Increment Circuit and Half Adders

• An increment circuit with n inputs and n1
  outputs computes binary value that is one larger
  than its input.

• It can be implemented using n linked half-adder
  circuits.
• to obtain a selectable incrementer replace the
  constant 1 input with a control input
• time for increment growswith number of bits

17
Addition Circuit and Full Adders

• Addition circuit with 2n inputs n1 outputs
  computes the binary sum of two input values.

• It can be implemented using n linked full-adder
  circuits.

• A full-adder can be built from 2 half-adders.

• This addition circuit is called a ripple carry
  adder
• takes time proportional to n to add two n bit
  numbers

18
Simulation of Adder Circuit
19
Binary Multiplication

• Binary multiplication is done much like decimal
  multiplication.

1101 multiplicand
1010 multiplier
1101
0000

• Requires 1 bit multipliers (AND gates) and
  addition circuits.
• Can speedup by rearranging so additions occur in
  parallel.

20
Incrementer with Carry Look-ahead

• Can speed up incrementer using carry lookahead.
• Compute carry out of each position directly from
  inputs.
• redundant AND operations, but faster
• Speed comparison
• assumptions 2 input gate has 1 ns delay, 3
  or 4 input gate has 2 ns delay, 5 to 8
  input gate has 3 ns delay, . . .
• 64 bit ripple carry incrementer needs 64 ns in
  worst-case
• 64 bit carry-lookahead incrementer needs 7 ns in
  worst-case
• So, whats the catch?
• carry lookahead uses 2000 simple gate
  equivalents
• inputs must drive many gates

21
More Scalable Carry Lookahead

• 64 bit version has 7 ns delay, about 380 gates
  for carry, fanout6.

22
Carry Lookahead Adder

• Ripple carry adder is too slow for fast addition
  of large values (typical computer uses 32 or 64
  bit arithmetic).
• To get a faster circuit, replace long carry chain
  with a shorter circuit. First separate carry
  logic in FA.

Let Gi be generate signal for bit i, Pi be
propagate signal and Ci be carry into bit
i. C2G1C1P1G1G0P1C0P0P1 and C3G2C2P2
G2(G1G0P1C0P0P1)P2 G2G1P2G0P1P2C0P
0P1P2 and so forth.
generate
propagate

• So high order carries can be generated with low
  delay, at the cost of more gates.

23
Simulation of Carry Lookahead Adder
24
More Scalable Lookahead Adder

• A more scalable lookahead adder can be obtained
  by writing the logic equations differently.
• Let G(i,j) be true if a carry is generated from
  within the bits i-j1 up to i G(i,j)Gi Gi-1Pi
  ??? Gi-j1Pi-j2???Pi
• Let P(i,j)Pi???Pi-j1.
• Now, we can also write,
• G(i,1)Gi P(i,1)Pi
• G(i,2)G(i,1)G(i-1,1)P(i,1) P(i,2)P(i,1)P(i-1,
  1)
• G(i,4)G(i,2)G(i-2,2)P(i,2) P(i,4)P(i,2)P(i-2,
  2)
• G(i,8)G(i,4)G(i-4,4)P(i,4) P(i,8)P(i,4)P(i-4,
  4)
• These equations lead directly to the design on
  the following page.

25
Lookahead Adder Schematic
Up to 22log2n gate delays.
Partial full adder
26
Linear Circuit Pattern

• Ripple-carry increment and addition circuits are
  examples of a common linear circuit pattern.
• copies of a common block with one or more
  signals between adjacent blocks

• Other circuits with similar pattern.
• 2s-complementer, maximum, comparison, count-ones,
  . . .
• Propagation delay for such circuits typically
  grows in proportion to number of blocks.
• Look-ahead versions can have propagation delays
  that grow with logarithm of number of blocks.

27
Modular and Signed Arithmetic

• If overflows are discarded, binary adders
  actually implement modulo arithmetic in which
  values wrap around circularly.
• to add AB, start at position for A and then
  count clockwise B positions
• standard addition algorithm does exactly this.

• Associating certain bit patterns with negative
  values yields signed arithmetic.
• Negate a given value by flipping all bits and
  adding 1.

28
2s Complement and Subtraction

• In 2s complement arithmetic with n bits
• the first bit represents the sign (0 for
  positive, 1 for negative)
• for positive numbers, the remaining n-1 bits give
  the magnitude in standard binary notation
• to convert a positive number to corresponding
  negative number, flip all bits and add 1
  (0011?110011101)
• to convert a negative number to corresponding
  positive number, flip all bits and add 1
  (1101?001010011)
• To subtract, take complement and add.
• 410-710 0100-0111 0100(-0111) 01001001
  1101 -310
• 2s complement is most popular method for
  representing negative numbers.
• requires no special subtraction circuit, just
  addition and complement

29
Adder-Subtracter

• When sub0, result is AB.
• When sub1
• bit flipper complements all bits of B
• adder sums and adds 1A-B A (-B) A
  (not(B) 1) A not(B) 1
• Takes just slightly more time than plain adder.

30
Alternative Negative Number Formats

• In 1s complement arithmetic, negate a valueby
  flipping bits (do not also add 1).
• gives two different representations for zero
• when adding two values, if carry out of
  mostsignificant digit, increment to obtain final
  sum
• comparable to 2s complement but not quite as
  simple

• In sign-magnitude arithmetic, left-most bit is
  sign and remaining bits give magnitude.
• most obvious representation for people
• does not allow negative numbers to bedirectly
  added
• requires separate subtraction hardware

31
Computer-Aided Design

• CAD tools are essential to the design of complex
  parts.
• Logic design
• schematic capture - interactive creation of logic
  diagrams
• hardware description languages - textual
  representation of circuit function
• Design verification
• logic simulation to check circuit behavior
  experimentally
• formal verification tools - automated correctness
  proofs and assertion checking
• timing analysis and simulation
• Implementation
• logic synthesis - convert high level spec. to low
  level gates
• circuit layout - placement of components, routing
  of wires
• details - clock distribution, power, pads, testing

32
Hardware Description Languages

• HDLs allow designers to work at a higher level of
  abstraction than logic gates.
• As with programming languages, HDL descriptions
  are compiled into a lower level representation.
• low level form can be simulated for logical
  correctness
• and, can be converted to a circuit specification
  using a library of primitive components and
  timing/area constraints
• But dont confuse hardware design with software.
• HDL descriptions must reduce to physical hardware
  that can be fit in the physical space available
  and meets timing specs.
• hardware designs are inherently parallel with
  many things going on at once
• on the other hand, software can be used to
  implement much more complex functions than
  hardware alone.

Read Sections 1,2 of VHDL Tutorial
33
VHDL Specification of Half Adder
library provides commonly used types and functions
Port declaration defines inputs and outputs.
STD_LOGIC type used for signals.
May have different implementations for a given
module.
CAD software simulates circuit operation.
Signal assignments occur simultaneously.
xor, and are built-in operators
34
VHDL Specification of Full Adder

• library IEEE
• use IEEE.STD_LOGIC_1164.ALL
• use IEEE.STD_LOGIC_ARITH.ALL
• use IEEE.STD_LOGIC_UNSIGNED.ALL
• entity fullAdd is
• Port (
• a, b, Ci in std_logic
• S, Co out std_logic )
• end fullAdd
• architecture a1 of fullAdd is
• begin
• S lt a xor b xor Ci
• Co lt (a and b) or (a and Ci) or (b and Ci)
• end a1

Compact port declarations
Complex logic expressions.
35
What Does VHDL Spec Mean?

• VHDL specifies a circuit, not sequential
  execution. So,
• architecture arch of fulladd is begin
• s lt (a xor b) xor Ci
• Co lt (a and b) or (a and Ci) or (b and Ci)
• end arch
• means

• So, what does this mean?
• architecture foo of bar is begin
• a lt 1 b lt a a lt 0
• end bar

36
Signal Assignments for Vectors

• Example
• entity foo is
• port(a in std_logic
• b in std_logic_vector(2 downto 0)
• c out std_logic_vector(3 downto 0))
• end foo
• architecture bar of foo is begin
• c lt a (b(0) and a) b(2 downto 1)
• end bar
• defines circuit

37
Conditional Signal Assignment

• Example
• c lt "0010" when a / b else
• "1101" when a '1' else
• "0100"
• means

• general form
• x lt
• v1 when f1(a1,b1,...) else
• v2 when f2(a2,b2,...) else
• v3 when f3(a3,b3,...) else
• ... else vN

• x lt
• (f1(a1,b1,...) and v1) or
• (not f1(a1,b1,...) and
• f2(a2,b2,...) and v2) or
• (not f1(a1,b1,...) and
• not f2(a2,b2,...) and
• f3(a3,b3,...) and v3) or
• ...

?
38
Selected Signal Assignment

• Example
• with x select
• c lt "0010" when "00" , "1101" when
  "01" "10" ,
• 1100" when others
• means

• Resulting circuit is more compact and faster than
  circuit produced by conditional assignment.

39
Important Characteristics of VHDL

• VHDL developed for circuit modelling
  simulation.
• allows specification of hardware behavior
  independent of implementation
• synthesis tools developed later
• not all VHDL specifications can be synthesized
• Signals correspond to wires in circuit.
• language also supports variables - useful in
  behavioral models, testbenches
• best to avoid variables in synthesizable models
  (except loop variables)
• Signal assignments define logic circuits.
• signals on left side of assignment change as
  signals on right side change (exceptions to be
  discussed later)
• not like sequential program execution
• Strong typing in VHDL.
• signal types in expressions must match exactly
• no automatic type conversions
• bit and integer are only built-in types
• extensive support for user-defined types, such as
  std_logic
• std_logic defines 9 values, including 0, 1 and
  undefined

40
Processes and if-then-else

• Example
• entity foo is port(
• a, b in std_logic
• c, d out std_logic_vector(3 downto 0))
• end foo
• architecture foo of bar is begin
• process (a, b) begin
• if a / b then
• c lt "0010" d lt "1100"
• elsif a '1' then
• c lt "1101" d lt a b "01"
• else
• c lt "0100" d lt "10" b a
• end if
• end process
• end foo

process block enables use of complex statement
types
sensitivity list must include all input signals
to process
note that c,d defined under all possible input
conditions - REQUIRED
41
Avoiding Unintended Storage

• If value of a signal is not specified for some
  condition, it means that signal is unchanged.
• Example
• process(a,b) begin
• if a '1' then
• x lt '0'
• elsif b '1' then
• x lt '1'
• end if -- x retains value when ab0
• end process
• Storage elements are required to implement
  circuit with the specified behavior.
• if one accidentally omits a condition for a
  signal, unintended storage elements are
  synthesized.
• Easy way to avoid unintended storage is to start
  process with assignment of default values to all
  signals assigned a value inside the process.

42
Default Values

• Example
• entity foo is port(
• a, b in std_logic
• c, d out std_logic_vector(3 downto 0))
• end foo
• architecture foo of bar is begin
• process (a, b) begin
• c lt "0100" d lt "10" b a
• if a / b then
• c lt "0010" d lt "1100"
• elsif a '1' then
• c lt "1101" d lt a b "01"
• end if
• end process
• end foo

initial assignments define default values for c
and d
What values are assigned to c, d if we rearrange
so if-then-else comes first?
43
For-loops

• entity adder8 is
• Port ( Cin in std_logic
• A, B in std_logic_vector(7 downto
  0)
• S out std_logic_vector(7 downto 0)
• Cout out std_logic)
• end adder8
• architecture arch1 of adder8 is
• signal C std_logic_vector(8 downto 0)
• begin
• process(A,B,C,Cin) begin
• C(0) lt Cin Cout lt C(8)
• for i in 0 to 7 loop
• S(i) lt A(i) xor B(i) xor C(i)
• C(i1) lt (A(i) and B(i)) or (A(i) and C(i))
• or (B(i) and C(i))
• end loop
• end process
• end arch1

For-loop defines multiple identical (or similar)
sub-circuits. Loop does not imply sequential
ordering of signal assignments.
Note separate carry signal for each stage
cannot re-assign values to one signal as in
sequential programs.
44
Case Statement

• Case statement provides convenient way to express
  alternatives that depend only on value of a
  single signal
• architecture a1 of foo is
• begin
• process(c,d,e) begin
• b lt '1' -- provide default value for b
• case e is
• when "00" gt a lt c b lt d
• when "01" gt a lt d b lt c
• when "10" gt a lt c xor d
• when others gt a lt '0'
• end case
• end process
• end a1
• Creates more efficient circuits than equivalent
  if-then-else.

others alternative is required even when all
logical alternatives are specified
45
VHDL Spec. for Simple Arithmetic Unit
entity alu is Port ( a, b in
std_logic_vector(3 downto 0) c in
std_logic_vector(2 downto 0) x out
std_logic_vector(3 downto 0) v out
std_logic) end alu architecture a1 of alu
is signal result std_logic_vector(4 downto
0) signal ax, bx std_logic_vector(4 downto
0) begin ax lt '0' a bx lt '0' b result
lt ax when c "000" else bx when c
"001" else (not ax)1 when c "010"
else (not bx)1 when c "011"
else axbx when c "100" else axbx when
c "101" else ax-bx when c "110"
else bx-ax x lt result(3 downto 0) v lt
'1 when (c "010" and a "1000") or (c
"011" and b "1000") or (c "100" and
result(4) '1') or (c "101" and a(3) b(3)
and a(3) / result(3)) or (c "110" and
a(3)/b(3) and a(3) / result(3)) or (c
"111" and a(3)/b(3) and b(3) /
result(3)) else '0' end a1
c0 means xa, c1 means xb, c2 means x -a,
c3 means x-b, c4 means xab (unsigned), c5
means xab (signed), c6 means xa-b, c7 means
xb-a
v bit signalsarithmetic error
46
VHDL Spec. for Simple Arithmetic Unit
entity alu is Port ( a, b in
std_logic_vector(wSiz-1 downto 0) c
in std_logic_vector(ctlSiz-1 downto 0)
x out std_logic_vector(wSiz-1 downto 0)
v out std_logic) end alu architecture a1
of alu is signal result std_logic_vector(wSiz
downto 0) signal ax, bx std_logic_vector(wSiz
downto 0) begin ax lt '0' a bx lt '0'
b with c select result lt ax when "000"
, bx when "001" , (not ax)1 when "010"
, (not bx)1 when "011" , axbx when
"100" , axbx when "101" , ax-bx when
"110" , bx-ax when others x lt
result(wSiz-1 downto 0) v lt '1 when (c
"010" and a "1000") or (c "011" and b
"1000") or (c "100" and result(wSiz)
'1') or (c "101" and a(wSiz-1) b(wSiz-1)
and a(wSiz-1) / result(wSiz-1)) or (c "110"
and a(wSiz-1)/b(wSiz-1) and a(wSiz-1) /
result(wSiz-1)) or (c "111" and
a(wSiz-1)/b(wSiz-1) and b(wSiz-1) /
result(wSiz-1)) else '0' end a1
c0 means xa, c1 means xb, c2 means x -a,
c3 means x-b, c4 means xab (unsigned), c5
means xab (signed), c6 means xa-b, c7 means
xb-a
v bit signalsarithmetic error
47
Alternate Architecture

• architecture arithuv_arch of arithuv is
• signal result STD_LOGIC_VECTOR(4 downto 0)
• signal ax, bx STD_LOGIC_VECTOR(4 downto 0)
• signal en_a, en_b, neg_a, neg_b STD_LOGIC
• begin
• process(a,b,c,en_a,en_b,neg_a,neg_b) begin
• en_a lt '1' en_b lt '1' neg_a lt '0' neg_b
  lt '0'
• v lt '0'
• case c is
• when "000" gt en_b lt '0'
• when "001" gt en_a lt '0'
• when "010" gt en_b lt '0' neg_a lt '1'
• if a "1000" then v lt '1' end if
• when "011" gt en_a lt '0' neg_b lt '1'
• if b "1000" then v lt '1' end if
• when "100" gt v lt result(4)
• when "101" gt if a(3) b(3) and result(3) /
  a(3) then
• v lt '1'
• end if

case statement specifies alternatives based on
signal value.
en_a high when a used to generate result. neg_a
high to produce -a or b-a.
others required when not all alternatives listed.
48
for i in 0 to 3 loop ax(i) lt (a(i) xor
neg_a) and en_a bx(i) lt (b(i) xor neg_b) and
en_b end loop ax(4) lt en_a and (a(3) xor
neg_a) bx(4) lt en_b and (b(3) xor
neg_b) result lt ax bx (neg_a or neg_b)
x lt result(3 downto 0) end process end
arithuv_arch
for-loop modifies a, b
extend a, b to 5 bits with correct sign

• Original architecture synthesizes redundant
  components.
• Alternative architecture uses single adder and
  disables or negates inputs to implement different
  operations.
• circuit uses about half as many circuit
  components as original
• synthesis report provides detailed description

49
Structural Spec. for 4 Bit Adder

• entity adder4 is port(
• A, B in std_logic_vector(3 downto 0) Ci in
  std_logic S out std_logic_vector(3 downto
  0) Co out std_logic)end adder4architecture
  a1 of adder4 iscomponent fullAdder
• port(A, B, Ci in std_logic S, Co out
  std_logic )end componentsignal C
  std_logic_vector(4 downto 0)begin
• C(0) lt Ci Co lt C(4)
• b0 fullAdder port map(A(0),B(0),C(0),S(0),C(1))
  b1 fullAdder port map(A(1),B(1),C(1),S(1),C(2))
  b2 fullAdder port map(A(2),B(2),C(2),S(2),C(3)
  ) b3 fullAdder port map(A(3),B(3),C(3),S(3),C(4
  ))
• end a1

Component definitions required in every
architecture using a component.
component statement used to form complex circuits
from simpler parts.
Positional association of signals. Explicit
assignment (AgtA(0)) also allowed.
50
Defining Constants

• To define constants for use by multiple entities,
  use separate package.
• package commonConstants is
• constant wordSize integer 8
• end package commonConstants
• library IEEE
• use IEEE...
• use work.commonConstants.all
• entity adder is
• port( A, B in std_logic_vector(wordSize-1
  downto 0)
• Ci in std_logic
• S out std_logic_vector(wordSize-1 downto
  0)
• Co out std_logic )
• end adder
• ...
• Local constants can be declared as part of each
  architecture.
• HDL bencher does not handle constants in packages
  correctly.
• use Options ?Map Package Constants/Defines

51
Structural Specs. using for-generate

• begin C(0) lt Cibg for i in 0 to 3 generate
  b fulladder port map(A(i),B(i),C(i),S(i),C(i1)
  ) end generate
• Co lt C(4)           end a1

for-generate makes it easy to generate adder of
any size. Note labels are required.