An Embedded True Random Number Generator for FPGAs

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An Embedded True Random Number Generator for FPGAs
Paul KohlbrennerLockheed Martin3201 Jermantown
RoadFairfax, VA 22030, USAPaul.W.Kohlbrenner_at_lmc
o.com
Kris GajGeorge Mason University4400 University
DriveFairfax, VA 22030, USAkgaj_at_gmu.edu

• Bebek, Jerry

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• Random numbers are an essential in ComS.
• and, just as problematic.
• There are several methods to generate them.
• Unfortunately, all these methods are
  deterministic.
• The Question HOW COULD A TOTALLY LOGICAL MACHINE
  GENERATE
• A RANDOM NUMBER?

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The Answer It Cant.
The only truly random number sources are those
related to physical phenomena such as the rate
of radioactive decay of an element or the
thermal noise of a semiconductor. BOTTOM
LINE Randomness is bound to natural phenomena. It
is impossible to algorithmically generate truly
random numbers.
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PSEUDO-VULNERABILITY
Pseudo-Random numbers are prone to being broken
into.
..and yes, it has happened.
It is not an impossible task to analyze patterns
in pseudo-random numbers. A 40-bit encryption
with algorithmically generated random numbers
could be broken in as little as 30 hours.
The Netscape 2.0 Attack Was An Example.
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FPGA Advantage In The Field
Near-ASIC encryption speeds Algorithm and
resource efficiencies In service algorithm
modification Low development costs
Parameter and algorithm eraser on intrusion
detection
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The Method Clock Jitter

• Jitter is variations in the significant instants
  of a clock.
• Jitter is nondeterministic (random)
• Jitter may have many sources
• semiconductor noise
• cross talk
• Power supply variations
• electro-magnetic fields
• Jitter may be characterized in several ways
• Period Jitter
• Amplitude Jitter

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Period Jitter (clock skew)
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Overall Design
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The Ring Oscillators
Uses Propagation Delay 130 MHz
x2
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The Sampler
One of the clock signals is used to sample the
other signal.
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The Output From The Sampler
Clock Skew (jitter) in between two clock signals
is used (e.g. sampled) to generate a totally
random bit. Note that clock skew will never be
uniform. Note that clock skew is NOT simple
out-out-phase ness.
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Jitter (detail)
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Good Speed Ratios

• Ring oscillators with closely matched frequencies
  require that a desired speed ratio must be
  achieved.
• What factors affect this achievement?
• Variation in CLB speed
• 7 difference between the slowest CLB and the
  fastest one
• Sensitive to temperature and difficult for
  measurement
• Variation in the frequency of an oscillator with
  the chip temperature
• Close placement
• To use a large number of oscillators

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Evidence of Jitter

• Clocks with jitter lead to randomness of output
  bit stream
• If signal S0 has a single length, the output
  will be deterministic (all 0s, or 1s or 0s and 1s
  with a repeating pattern)
• Evidence Variation in the cycle lengths of
  Oscillators ? Variation in the cycle length of
  the signal S0

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Evidence of Jitter (details)
Frequency 130MHz
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Bias in the Output

• Ideal Output 1s and 0s are evenly and randomly
  distributed.
• Output with bias 1s more likely than 0s, or vice
  versa
• The sources of bias
• The limited number of difference bit length of S0
  signal
• Occasional meta-stable output from the sampling
  flip-flop, (using a buffer can alleviate this
  problem)

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Reduction of Bias

• XOR of successive pairs of bits
• Example
• P(X1)2p(1-p),
• P(X0)p2(1-p)2
• (p is the probability of 1s)
• A von Neumann corrector
• NOTE
• Limitation no correlations in the output bit
  stream
• Disadvantage reduction of the output bit rate

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Output Bit generation speed
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Experimental Environment

• SLAAC-1V board with three Xilinx Virtex XCV1000
  FPGA
• Synplify V7.2
• Xilinx ISE 4.2
• NIST Statistical Test Suite for Random and
  Pseudorandom Number Generator for Cryptographic
  Applications

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Experimental Results
P-value the probability that a perfect random
number generator would have produced a sequence
less random than the sequence that was tested
The larger, the better.
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Future Work

• Increasing output bit rate by
• Increasing the speed of ring oscillators
• Generating S0 signal from both rising and falling
  edge of the clock
• Increasing the number of oscillators to solve
  problems in finding matched CLBS
• Adding a counter to S0 signal for real time
  noise-failure alarm

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Conclusion

• The implementation is useful addition to the
  cryptographic systems using FPGA
• No special requirement within FPGA increases the
  universal of the design

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Questions

• ???