Methods to Differentiate Mil/Aero Solutions Using FPGAs BOF session W

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Methods to Differentiate Mil/Aero Solutions Using
FPGAsBOF session W Focus on verification

• Dan Gardner

Final MAPLD BOF Presentation
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Requirements for FPGA Software in Mil/Aero

• Cost effective delivery of mission performance
• Initial Creation
• Cost and speed of design
• Predictable time to market at fixed cost
• Fast iterations
• Timing and system closure
• Complete Verification
• Commercial FPGA often skips many verification
  steps
• Some Mil/Aero applications have additional
  considerations
• Maintenance of Project
• Cost of life cycle maintainability of design
• Support of standard platforms
• Support Mil-preferred devices, documentation and
  flows

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Technologies to Consider

• All technologies listed below are required to
  build a complete methodology and will be covered
• This presentation will essentially focus on the
  unique requirements of Mil/Aero FPGA
  applications
• Rule checker with platform-independent coding
  styles
• Design management
• RTL physical synthesis
• I/O design with integration path to PCB
• System-level design
• Verification
• Electronic System-Level (ESL) Overview
• Assertion based (CDC to validate SEU protection)
• Coverage driven
• Clock domain crossing (CDC)
• Embedded systems

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Verification Technology

• Rule checker with platform-independent coding
  styles
• Design management
• Verification
• Electronic System-Level (ESL) Overview
• Assertion based (CDC to validate SEU protection)
• Coverage driven
• Clock domain crossing (CDC)
• Embedded systems

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Rule Checkers
Static Design Checking for VHDL/Verilog RTL

• Encapsulate knowledge
• Expect built-in checks from standard sources
• Reuse Methodology Manual
• FPGA vendor recommendations
• Must allow quick customization for your own
  checks
• Use Early and Often
• Perform checking interactively or in batch
• Understand the causes of violations
• Easily interact, organize, track violations
• Interactively trace fix violations
• Share knowledge
• Share checks with the team/company
• Allow any designer to apply accumulated knowledge
• Export results for reporting

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Rule Checking Project Management

• HDL Designer Manage Text, Graphics, VHDL,
  Verilog, SystemC, SystemVerilog, PSL, C/C,
  Scripts, Revision Control, Automated Design
  Documentation

Process Automation
Version Management
PCB I/O Designer
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Verification Technology

• Rule checker with platform-independent coding
  styles
• Design management
• Verification
• Electronic System-Level (ESL) Overview
• Assertion based (CDC to validate SEU protection)
• Coverage driven
• Clock domain crossing (CDC)
• Embedded systems

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Design Languages Tasks
Language
Task
Text / UML
Requirements
HVLs extend accelerate the RTL design process
and enable RTL designers to cross the chasm to
system level design
C/C Untimed SystemC
Algorithm Exploration
Transaction Level SystemC
Architecture Analysis
System Verilog
Verification
Assertions PSL/SVA
VHDL Verilog
RTL Design
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Abstraction Drives Design Productivity
Implementation
Simulation
Source
Algorithmic C
Untimed TLM SystemC
Timed TLM SystemC
Cycle Accurate SystemC
RTL
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Automatic Generation of Verification
Infrastructure
Original C Testbench

• Facilitates the verification of the synthesized
  design
• The original C testbench can be reused to
  verify the design
• RTL or cycle accurate
• SystemC, VHDL or Verilog
• Transactors convert function calls to pin-level
  signal activity
• Pushbutton verification solution includes
  Makefiles and simulation scripts

Transactor
RTL
Original C Algorithm
Transactor
Comparator
Golden results
DUT results
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Exhaustive Algorithm VerificationWith Automated
Real Time Prototypes
?

• Quickly produce RTL code from algorithmic
  specifications
• Regardless of the quality of the architecture
• Run RTL synthesis and PR with integrated tool
  flows
• Validate the functional correctness of the
  algorithm on FPGA prototyping boards
• Architecture optimization can be pursued in
  parallel

Algorithms
C Code Constraints
Catapult C Synthesis
Precision RTL Synthesis
RTL Code Constraints
FPGA Vendor PR
Netlist Constraints
?
Prototyping
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Catapult C Addresses the ESL Synthesis Challenge
NEW Catapult C Design Flow
Algorithm Functional Description

• Safer design flow
• Shorter time to RTL
• More efficient methodology
• Design optimized to system requirements through
  incremental refinement

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Methodology Explosion Targeting Verification

• Assertion-based verification
• Functional coverage
• Constrained-random testing
• Coverage-driven verification
• Dynamic-formal verification
• Transaction-level verification
• Model checking
• And more . . .

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Common Verification Methodologies
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SystemVerilog for Verification

• SystemVerilog is a complete Verification Language
• Can be used with VHDL
• Stimulus generation capabilities
• Dynamically configurable constrained-random value
  generation
• Ability to generate constrained-random stimulus
  sequences
• Ability to randomly select control paths (test
  scenario selection, etc.)
• Functional coverage modeling
• Measure the verification quality and test
  effectiveness
• Dynamic reactivity with constrained-random
  stimulus generation
• Assertion-based verification
• Property specification
• Assertion coverage monitoring
• High-level modeling (programming) capabilities
• Efficiently and effectively model the operational
  environment
• Develop reusable verification environments

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Assertion-Based VerificationAssertions Enable
Higher Quality Designs

• Assertions provide observability for higher
  complexity designs
• ABV makes assertions a key element, ensuring that
  design properties are not violated
• Assertions describe (un)desired behavior
• Assertions dramatically shorten debug and repair
  time
• Assertions stay on during block, chip and
  system-level tests
• Finds bugs you werent looking for

Reference Model
Bus Monitor
Bus Monitor
Assertion Checkers
Assertion Checkers
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Expect Widespread Use of Coverage-Driven
Verification

• PSL and SystemVerilog provide coverage constructs
• Simulators integrating functional coverage to
  improve performance and debug
• New test strategies require functional coverage
• Random and constrained random tests need coverage
  to determine what they tested

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Clock-Domain Crossings

• Incorrect handling of Clock-Domain Crossing (CDC)
  signals is the 2nd major cause of re-spins
• Traditional verification techniques do not work
  for CDC signals
• CDC problems are subtle, will occur in hardware,
  and are complex to debug

Assertion Synthesis automates CDC verification,
significantly reducing the risk of CDC-related
silicon re-spins
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Complete Verification Flow
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Verification Technology

• Rule checker with platform-independent coding
  styles
• Design management
• Verification
• Electronic System-Level (ESL) Overview
• Assertion based (CDC to validate SEU protection)
• Coverage Driven
• Clock domain crossing (CDC)
• Embedded systems

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Platform FPGAs Need a Complete Flow
Hardware
Software
Platform Studio IDE
ASAP
Platform Exp
Inventra
Precision Synthesis
CodeLab
Stacks
Modelsim
Seamless
ISS
BSP
ISE Tools
Microtec
XRAY
Nucleus
Chipscope
SW-HW OnChip Debug
PCB, Signal Integrity Tools
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HW/SW Co-verification Faster Iteration Loop
Without Co-verification
With Co-verification
HDL Entry
HDL Entry
HDL Compile
Synthesis
Implementation
Download Bitstream Into FPGA

• Supports
• Edit/Compile/Verify
• Eliminates
• Edit/Synthesize/ Implement/Download/Verify
• Promotes Superior Visibility and Control

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Summary

• With engineers from software, hardware and system
  disciplines all converging on FPGAs, it is
  important to focus on the methods that can help
  differentiate your solution from others.
• It is necessary to use all the basic verification
  and design tools, but there are new technologies
  emerging that can better address the unique
  requirements of Mil/Aero applications.