Alex Katsnelson, Vadim Tokranov, Mike Yakimov, Ren Todt, and Serge Oktyabrsky

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Hybrid Integration of III-V VCSEL Arrays on Si
Platform
Alex Katsnelson, Vadim Tokranov, Mike Yakimov,
René Todt, and Serge Oktyabrsky School of
Nanosciense and Materials and UAlbany Institute
for Materials, University at Albany - SUNY
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A novel integration protocol for bonding of III-V
optoelectronic components such as LEDs, VCSELs
and photodetectors on Si platform was proposed.
The III-V structures are grown homoepitaxialy,
and the processing of the device mesas with
metallization is completed on the III-V
substrate. The hybrid integration involves
self-alignment of the device mesas with the
recessed base in the polyimide/Si structure,
In-Sn solder bump bonding, subsequent removing
of the substrate by wet etching or epitaxial
liftoff. MBE-grown reversed VCSEL structure was
used for manufacturing of the integrated devices
using this novel protocol. An AlAs etch stop
layer was imbedded into the structure for
subsequent substrate removing. The array of the
3D devices was fabricated using reactive ion
etching in Cl2/BCl3 ECR plasma. The array to be
bonded with Si consists of the columns etched
down below the VCSEL active area to provide the
bed for the double-level metallization. The
simulation of thermal behavior of this
integration scheme was performed using finite
element analysis and revealed adequate heat
dissipation. This reduction of heating leads to
enhance the optorlectronic devices performance
and increase their lifetime. At present, we have
demonstrated the integration of a scaled up
VCSEL structure with aperture size from 75 to 100
mm.
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Needs and Motivation

• Reliable technology for integration of III-V
  compounds with Si electronics
• Transfer massive arrays of III-V devices onto Si
  platform
• Choose the most reliable, low-temperature (lt400
  0C) and inexpensive method

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Heteroepitaxial Growth vs. Hybrid Integration

• Heteroepitaxy
• Advantages
• No processes of substrates alignment and bonding
• Low Si substrate cost
• Disadvantages
• High defect density
• High growth temperature (gt400 ?C )
• Lattice mismatch and thermal expansion
  coefficient mismatch induced stress
• Incompatible technologies of III-V and Si device
  processing

• Hybrid integration
• Advantages
• Low defect density in homoepitaxial film
• High reliability of the devices
• Complete processing of III-V devices on GaAs
  wafer
• Disadvantages
• Challenging alignment and film-to-substrate
  bonding protocols
• High GaAs substrate cost

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Hybrid Integration and Packaging

• Hybrid integration of III-V device arrays on Si
  chip using an imbedded flip-chip approach allows
• Complete processing of III-V devices on GaAs
  wafer
• Single side metallization on GaAs wafer
• Transfer of massive array of III-V devices on a
  dye or wafer level.
• Etching out or epitaxial lift-off of GaAs
  substrate to separate the optical devices to
  avoid thermal stresses in hybrid structures
• Alignment tolerance
• Wafer-level testing

• Major Problems
• Alignment
• Thermal expansion compensation
• Heat dissipation

• Major methods
• Wafer bonding
• Epitaxial lift-off
• Flip-chip bonding

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MBE-Grown Reversed VCSEL Structure
FIB cross-section of grown VCSEL structure
n-DBR
p-DBR

• Bottom DBR - semitransparent
• N-type doping Si p-type doping Be or C
• AlAs epitaxial sacrificial layer for separation
  of components

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Process Flow, Step 1 n-contact deposition
Optical micrograph of VCSEL array top contacts
Stack of Au-Ge-Ni-Au 66 nm-32 nm-30 nm-200
nm
200 mm
40 mm

• Au-Ge-Ni-Au stack for low resistivity ohmic
  contact to n-GaAs
• Contact deposition prior to RIE provides
  self-alignment etching process
• AZ-5214E dual-tone photoresist is used for
  lift-off process

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Cl2 RIE of mesa
Process Flow, Step 2
Etched VCSEL mesa

• Gold is used as a mask for RIE process
• RIE in Cl2/BCl3 ECR plasma
• Etching down to half of p-DBR
• End-point detection using interference from DBR

Reflection oscillations during the etch
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p-contact deposition
Process Flow, Step 3
Pt-Ti-Pt-Au 10 nm-40 nm-10 nm-200 nm
FIB cross-section of VCSEL mesa edge with
two-level metallization

• Pt-Ti-Pt-Au stack for low resistivity ohmic
  contact to p-GaAs
• AZ-5214E dual-tone photoresist is used for
  lift-off process

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Selective Wet Etch Down to Etch-Stop Layer
Process Flow, Step 4
Top view of etched VCSEL mesa
Selective etching

• 51 (??????2)2. ?(??)???? H2O2 wet chemistry
• High selectivity for AlAs
• Last processing step on GaAs substrate

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Process Flow, Step 5 Patterning of Polyimide
by O2 RIE
Polyimide/Au bed for 15mm VCSEL
Top view of processed Si structure
Cr-Au contacts
Polyimide

• Gold is used as a mask for RIE process
• Polyimide compliant interposer to adjust for the
  VCSEL/bed hight difference

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Process Flow, Step 6 InSn Solder Bumps
Sputtering
Top Au-contact
Bottom Au-contact
InSn 90/10 solder

• Good adhesion properties of InSn alloy
• Ar magnetron sputtering is used for this
  process
• Reflow temperature 150 0C

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Process Flow, Steps 7,8,9 Die Attach with
Solder Bumps and separation of III-V components

• Low InSn melting temperature allows to connect
  GaAs and Si parts without overheating
• Hybrid integration involves self-alignment of the
  device mesas with the recessed base in the
  polyimide/Si structure
• Wax protects edges of the devices during GaAs
  etching
• Etching of the AlAs layer by BHF
• Separation of devices to reduce thermal stresses

wax
Si Substrate
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Heat Dissipation in Hybrid-Integrated Devices

• Major issues
• Optimization of materials and design to increase
  heat dissipation
• Reliability of devices

Finite Element Analysis

• Results of simulation
• VCSEL aperture size 6 mm
• Power dissipation 2 mW
• Overheating 24 0C
• Thermal contact of VCSEL with Si substrate allows
  adequate heat sink.

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Conclusions

• The novel integration protocol for bonding of
  III-V optoelectronic components such as LEDs,
  VCSELs and photodetectors on Si platform was
  proposed
• The simulation of thermal behavior of this
  integration scheme was performed using finite
  element analysis and revealed adequate heat
  dissipation