IEEE 2015 VLSI SOFT-CORE EMBEDDED-FPGA BASED ON.pptx

1
SOFT-CORE EMBEDDED-FPGA BASED ON MULTISTAGE
SWITCHING NETWORKS A QUANTITATIVE ANALYSIS 
2
 ABSTRACT

• Our proposed is an embedded field programmable
  gate arrays (eFPGA) can provide modern
  systems-on-a-chip (SoCs) with the flexibility
  required to face the growth of nonrecurring
  engineering and manufacturing costs. On the other
  hand, SoC designers usually perceive eFPGAs as
  area-hungry IPs with poor flexibility in terms of
  performance, power and area tradeoff since they
  are typically available as custom-designed hard
  macros. In this scenario, technology scaling is
  allowing designers to reduce the impact of the
  eFPGA area gap, while effective exploitation of
  all the technology options (e.g., the transistor
  threshold) entails moving toward soft-core eFPGAs
  to match specific application needs.

3

• In this paper, we propose an look-up table-based
  soft-core eFPGA featuring a synthesizable and
  parametric architecture. A key point of our
  proposal is that we have adopted a multistage
  switching network (MSSN) to implement the
  programmable interconnect, since this ensures a
  synthesizable and congestion-free architecture.
  Quantitative evaluation of our eFPGA shows a
  significantly wide design-space available on very
  different technologies (we experimented
  STMicroelectronics CMOS 65 nm and BCD9s 0.11 µm).
  Application-driven evaluation showed how for a
  fixed eFPGA size (i.e., number of logic blocks)
  different configurations of the MSSN allow
  designers to speed up performance by 20/60, as
  well as to maximize the computational density for
  a given area budget.

4
EXISTING SYSTEM

• The overall number of levels to be crossed to
  connect inputs to outputs represents the latency
  of the network. Depending on their topology,
  MSSNs can be classified as non blocking, if any
  connection can be realized, or blocking, if there
  are paths that cannot be satisfied for either
  unicast or multicast connections. Greater
  complexity also brought congestion issues
  especially in the middle of the devices and these
  were addressed by either increasing channel size
  or adopting non uniform channels with the
  drawback, in both cases, of a significant area
  increase.

5
PROPOSED SYSTEM

• Our proposes a soft-core eFPGA template and
  quantitatively analyzes the opportunities given
  by a fully synthesizable approach, following an
  implementation flow based on standard-cell
  methodology. A key point of the eFPGA softcore is
  that it adopts a multistage switching network
  (MSSN) as the foundation of the programmable
  interconnects. This can avoid, or at least limit,
  the need for custom circuit design, since the
  network can be efficiently synthesized and
  optimized through a standard cell-based
  implementation flow, while it ensures a
  congestion-free network topology, thanks to the
  intrinsic properties of some specific MSSNs.

6
SOFTWARE REQUIREMENTS

• Xilinx ISE Design Suite 13.1
• Cadence-RTL Complier
• Cadence- encounter