VLSI Final Design Report EE715 Spatial Filter Coefficients ROM

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VLSI Final Design ReportEE715Spatial Filter
Coefficients ROM

• James OBoyle
• Pat Friel

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Design Progress Modification

• 0 Bit Cell modified
• 1 Bit Cell modified
• Pull-Up Network
• Array modified
• Buffer Network modified
• Timing Functionality
• Problems

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The 0 Bit Cell modified
In our design, we modified our cells and did a
complete change of various things. The zero bit
cell was modified by switching metal2 to metal1
and vice versa. You will see later on why this
choice was made.
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The 1 Bit Cell
The one bit cell was also changed the same way to
be able to fit with the zero bit cell. The new
cell also uses one less via connection.
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Forming The Array

• This next slide shows how our single array cells,
  which store 1 or 0 bits, fit together to form the
  array.
• The metal2 layer in the vertical direction on the
  right is the output of the array which is brought
  down to our inverter network to invert and boost
  the output when conducting to 4.8V.
• The metal1 layer on top is the connection to the
  gates of the array transistors. This connection
  comes from the decoder which selects the
  appropriate row in the array.
• The metal1 layer on bottom is the ground line for
  the NMOS array transistors.
• We used as little polysilicon as possible to cut
  down resistance at the gates of the transistors.

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Forming The Array
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The Pull-Up Network

• The Pull-Up Network allows the array transistors
  to conduct when the decoder output selects a
  certain row of transistors.
• The output of the decoder sends a logic 1, or 5
  volts, to the row it selects.
• All the transistors in that row will conduct
  sending a voltage down to the Inverter Network.
• We are using a Length of 2 Lambda, and a Width of
  5 Lambda for the PMOS pull-up transistors.

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The Pull-Up Network
The pull-up transistor widths are the same width
as the NMOS array transistors 5 lambda. We
achieved the best simulation results with this
configuration rather than the typical 3/2 ratio.
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Array modified

• The array is has been modified from the original
  configuration of 64x16 to a 16x16. The reason for
  this is because of various LVS errors that we
  were not able to fix.
• The array was programmed with some dummy data
  which is on the next slide.
• We are designing the ROM with a 16 bit output
  instead of 8 bits. We are not able to go to a 32
  bit output because of our 40 pin restriction.
  This would mean we would only have 3 left over
  pins for power and ground. We need at least two
  for each. 24 bit final output is possible for
  last minute change.
• Current complete size is a 16x16 bit ROM
• The slide after next shows a close-up picture of
  the ROM array we have designed.

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ROM Data

• The following binary numbers have been
  programmed
• 0000000000000001
• 0010001101001011
• 1001010001001010
• 0100100010100101
• 0001001000110010
• 1100100101001011
• 0010101000100100
• 0100010101001001
• 0001100001010101
• 1010001100100010
• 0100010011000100
• 1000110100100011
• 1011000010010101
• 0101101101010001
• 1010010110100110
• 0011010101010001

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Array Layout
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The Inverter Network

• Our inverter network is a series of inverters
  with modified transistor widths. These widths for
  both PMOS and NMOS are 8 lambda.
• This network inverts, strengthens the signal sent
  from the array and produces it on the output pins
  of the chip.
• The next slide shows a close-up picture of our
  inverter schematic and layout of the network.

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The Inverter Network
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The Inverter Network
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The Decoder

• Instead of using a 6 to 64 decoder as originally
  planned, we are now using a 4 to 16 decoder to
  access our 16x16 ROM array. This is again due to
  the LVS errors we could not fix in our earlier
  design. Also our 6 to 64 decoder just barely fit
  on the chip with the array.
• Our decoder is five, 2 to 4 decoders cascaded. We
  are using an enable on the decoders to do this.
• In the auto-layout of the decoder we had all the
  ports be placed on the right for easy connection
  to the array.
• The next slides shows the decoder schematic, and
  auto-layout.

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Decoder Schematic
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Decoder Layout
18
Decoder LVS
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Complete System

• Implementation of our complete system is shown on
  the next few slides.
• They show the decoder attached to the array and
  inverter network in schematic view and in layout
  view.
• Also the projected number of pins in use by this
  complete system is 25 pins.
• 16 pins for the output, 4 pins for address, 1
  enable pin, 2 Vdd pins, and 2 Gnd pins.

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System Truth Table
Input Output A3 A2 A1
A0 F15 -gt F00
0000000000000001 0010001101001011 1001010001001010
0100100010100101 0001001000110010 110010010100101
1 0010101000100100 0100010101001001 00011000010101
01 1010001100100010 0100010011000100 1000110100100
011 1011000010010101 0101101101010001 101001011010
0110 0011010101010001

• 0000
• 0001
• 0010
• 0011
• 0100
• 0101
• 0110
• 0111
• 1000
• 1001
• 1010
• 1011
• 1100
• 1101
• 1110
• 1111

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Complete Schematic View
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Complete Layout View
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Timing Functionality

• Our largest bottleneck in the design will be our
  decoder.
• The decoder uses ADK logic found in Mentor
  Graphics library.
• Most of our design is done in full custom layout.
  The decoder will be one of the few auto placed
  components.

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Decoder Simulation
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ROM Simulation
This is a simulation of the complete ROM system.
What is shown is an input of 0000 and 1001 pulsed
into the address line. When 0000 is input, we get
an output of 0000000000000001, and when 1001 is
input, then we get 0100010011000101 as we
expected.
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Problems Future Modifications

• Trouble with IC Station auto placing our 6 to 64
  decoder.
• Unfixable LVS errors, connectivity errors, and
  port matching errors.
• 64x16 array very large and slowed simulation down
  a lot.
• Extra unused pins on the chip will be connected
  at various places throughout our design.
  Projected 7 15 extra pins on final chip design.
• Mach TA Simulation and Pad Frame Connection to be
  finished.
• Report to be finished.

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Timeline (As of Now)

• September October November December

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VLSI Design

• -James OBoyle
• -Pat Friel