EE5342 Semiconductor Device Modeling and Characterization Lecture 24 Spring 2004

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EE5342 Semiconductor Device Modeling and
CharacterizationLecture 24 - Spring 2004

• Professor Ronald L. Carter
• ronc_at_uta.edu
• http//www.uta.edu/ronc/

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Ideal 2-terminalMOS capacitor/diode
Vgate
conducting gate, area LW
-xox
SiO2
0
y
0
L
silicon substrate
tsub
Vsub
x
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Band models (approx. scale)
metal
silicon dioxide
p-type s/c
Eo
Eo
qcox 0.95 eV
Eo
qcSi 4.05eV
qfm 4.1 eV for Al
Ec
qfs,p
Eg,ox 8 eV
Ec
EFm
EFi
EFp
Ev
Ev
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Flat band condition (approx. scale)
Al
SiO2
p-Si
q(fm-cox) 3.15 eV
q(cox-cSi)3.1eV
Ec,Ox
qffp 3.95eV
EFm
Ec
Eg,ox8eV
EFi
EFp
Ev
Ev
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Equivalent circuitfor Flat-Band

• Surface effect analogous to the extr Debye length
  LD,extr eVt/(qNa)1/2
• Debye cap, CD,extr eSi/LD,extr
• Oxide cap, COx eOx/xOx
• Net C is the series comb

COx
CD,extr
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Accumulation for Vgatelt VFB
Vgatelt VFB
-xox
SiO2
EOx,xlt0
0
holes
p-type Si
tsub
Vsub 0
x
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Accumulationp-Si, Vgs lt VFB
Fig 10.4a
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Equivalent circuitfor accumulation

• Accum depth analogous to the accum Debye length
  LD,acc eVt/(qps)1/2
• Accum cap, Cacc eSi/LD,acc
• Oxide cap, COx eOx/xOx
• Net C is the series comb

COx
Cacc
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Depletion for p-Si, Vgategt VFB
Vgategt VFB
-xox
SiO2
EOx,xgt 0
0
Depl Reg
Acceptors
p-type Si
tsub
Vsub 0
x
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Depletion forp-Si, Vgategt VFB
Fig 10.4b
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Equivalent circuitfor depletion

• Depl depth given by the usual formula xdepl
  2eSi(Vbb)/(qNa)1/2
• Depl cap, Cdepl eSi/xdepl
• Oxide cap, COx eOx/xOx
• Net C is the series comb

COx
Cdepl
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Inversion for p-SiVgategtVThgtVFB
Vgategt VFB
EOx,xgt 0
e- e- e- e- e-
Acceptors
Depl Reg
Vsub 0
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Inversion for p-SiVgategtVThgtVFB
Fig 10.5

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Approximation conceptOnset of Strong Inv

• OSI Onset of Strong Inversion occurs when ns
  Na ppo and VG VTh
• Assume ns 0 for VG lt VTh
• Assume xdepl xd,max for VG VTh and it doesnt
  increase for VG gt VTh
• Cd,min eSi/xd,max for VG gt VTh
• Assume ns gt 0 for VG gt VTh

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MOS Bands at OSIp-substr n-channel
Fig 10.9
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Equivalent circuitabove OSI

• Depl depth given by the maximum depl xd,max
  2eSi2fp/(qNa)1/2
• Depl cap, Cd,min eSi/xd,max
• Oxide cap, COx eOx/xOx
• Net C is the series comb

COx
Cd,min
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MOS surface statesp- substr n-channel
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n-substr accumulation (p-channel)
Fig 10.7a
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n-substrate depletion(p-channel)
Fig 10.7b
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n-substrate inversion(p-channel)
Fig 10.7
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Values for gate workfunction, fm
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Values for fmswith metal gate
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Values for fmswith silicon gate
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Typical fms values
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Flat band with oxidecharge (approx. scale)
Al
SiO2
p-Si
lt--Vox--gt-
q(Vox)
Ec,Ox
q(ffp-cox)
Ex
q(fm-cox)
Eg,ox8eV
Ec
EFm
EFi
EFp
q(VFB)
Ev
VFB VG-VB, when Si bands are flat
Ev
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Flat-band parametersfor n-channel (p-subst)
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Flat-band parametersfor p-channel (n-subst)
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Inversion for p-SiVgategtVThgtVFB
Vgategt VFB
EOx,xgt 0
e- e- e- e- e-
Acceptors
Depl Reg
Vsub 0
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Approximation conceptOnset of Strong Inv

• OSI Onset of Strong Inversion occurs when ns
  Na ppo and VG VTh
• Assume ns 0 for VG lt VTh
• Assume xdepl xd,max for VG VTh and it doesnt
  increase for VG gt VTh
• Cd,min eSi/xd,max for VG gt VTh
• Assume ns gt 0 for VG gt VTh

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MOS Bands at OSIp-substr n-channel
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Computing the D.R. W and Q at O.S.I.
Ex
Emax
x
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Calculation of thethreshold cond, VT
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Equations forVT calculation
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Fully biased n-MOScapacitor
VG
Channel if VG gt VT
VS
VD
EOx,xgt 0
e- e- e- e- e- e-
n
n
p-substrate
VsubVB
Acceptors
Depl Reg
y
0
L
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MOS energy bands atSi surface for n-channel
Fig 8.10
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Computing the D.R. W and Q at O.S.I.
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Qd,max and xd,max forbiased MOS capacitor
Fig 8.11
xd,max (mm)
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Fully biased n-channel VT calc
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n-channel VT forVC VB 0
Fig 10.20
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References
Semiconductor Physics Devices, by Donald A.
Neamen, Irwin, Chicago, 1997. Device
Electronics for Integrated Circuits, 2nd ed., by
Richard S. Muller and Theodore I. Kamins, John
Wiley and Sons, New York, 1986