CSE246 Adder

1
CSE246Adder Part I

• Instructor
• Prof. Chung-Kuan Cheng

2
Framework

• Adder Design Specification
• Half/Full adder
• Carry ripple adder
• Adder Design Optimization
• Circuit level Asynchronous adder, Manchester
  adder
• Logic level carry look adder, Lings adder,
  etc
• Algorithm level prefix adders
• Generic parallel prefix adder optimization using
  dynamic programming
• Zero-deficiency prefix adder
• Function level carry skip adder
• Multi-operand Addition

3
Half Adder

• Half Adder
• half means no carry-in
• Input xi, yi
• Sum si xi?yi
• Carry out ci1 xiyi
• Notation
• ? means logical XOR
• means logical OR
• Juxtaposition means logical AND

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Full Adder

• Input xi, yi and carry-in ci
• Output
• si xi?yi?ci
• ci1 xiyi ci(xiyi)
• xiyi ci(xi?yi)

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Ripple Carry Adder
x0 y0 c0/cin
x1 y1
xn-1 yn-1
ci-1
. . .
c1
c2
Cout/cn
s0
s1
si-1

• Overflow flag cn?cn-1

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Understanding Carry Ripple Chain

• Carry generation signal
• gi xiyi
• Carry propagation signal
• pi xi?yi
• Carry annihilation signal
• ai (xiyi)
• Carry ripple in terms of p,g
• ci1 gi pici
• In practice, we might use
• ti xiyi pigi and ci1gitici

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Carry Ripple using (g,p) signals

• Consider the (g p) chain
• break the long paths

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Circuit level optimization

• Manchester Adder concept

xiyi xiyi xiyi xiyi
00 01 10 11
gi 0 0 0 1
Pi 0 1 1 0
ai 1 0 0 0
One and only one of gi, pi, and ai will be 1
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Circuit Level Optimization

• Manchester Adder static logic implementation

(gi)'
ci1
ci
pi
ai
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Circuit level optimization

• Manchester adder dynamic logic implementation
• precharge in 1st half cycle
• Evaluation in second half cycle

evaluation
precharge
Q
Time ?
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Logic level optimization

• Carry look ahead adder
• Instead of generating carries bit-by-bit, try to
  look ahead to generate a group of consecutive
  carries simultaneously
• Use logic manipulation to save hardware
• Recursively unroll cigi-1pi-1ci-1
• cigi-1pi-1gi-2pi-1pi-2ci-2
• cigi-1pi-1gi-2pi-1pi-2gi-3pi-1pi-2pi-3gi-4pi-
  1pi-2 pi-3pi-4ci-4

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Logic level optimization

• Lings adder
• Notice gigipi
• ci pi-1(gi-1gi-2pi-2gi-3pi-2pi-3gi-4pi-2
  pi-3pi-4ci-4)
• Use ti instead of pi
• citi-1(gi-1gi-2ti-2gi-3ti-2ti-3gi-4ti-2ti-3ti
  -4ci-4)
• Define the expression in parenthesis to be hi
• ci ti-1hi
• hi gi-1gi-2ti-2gi-3ti-2ti-3gi-4ti-2ti-3ti-4t
  i-5hi-4

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Asynchronous Adder

• Carry completion detection

ci bi Remark
0 0 Not complete
1 0 Complete
0 1 Complete
1 1 Dont care
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Group (G,P) signals

• Generating g32 and g32

g3
g2
p3
p2
g1
p1
C4
g3
p3
g2
p2
C1
g32
p32
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Group (G,P) signals

• Generating g10 and p10

g3
g2
p3
p2
g1
p1
C4
g1
p1
cin
cin
g10
p10
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Group (G,P) signals

• Generating g30 and p30

p3
g2
p2
g3
G32
P32
p32
g32
g10
g1
p1
g30
cin
p10
g10
p30
p10
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Group (G,P) signals

• g4 p4 ( g3 p3 ( g2 p2 ( g1 p1 ( g0 p0
  cin ) ) ) )
• g4 , p4 g3 , p3 g2 , p2 g1 , p1 g0
  , p0 cin
• g4p4g3 , p4p3 g2p2g1 , p2p1 g0
  , p0cin
• g4p4g3p4p3(g2p2g1) , p4p3p2p1 g0 ,
  p0cin
• g4p4g3p4p3(g2p2g1)(p4p3p2p1)g0 , (p4p3p2p1)
  p0cin

g43
p43
g21
p21
g41
p41
coutg40
p40
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Parallel Prefix Adder

• What is parallel prefix problem?
• How binary addition is modeled as a parallel
  prefix problem?

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Parallel Prefix Problem (PPP)
Given n inputs which can
be either scalars or vectors, and an arbitrary
associative operator , compute the products


for
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Parallel Prefix Problem

• Direct example is prefix sum problem
• is simply natural addition
• yi xixi-1x1 for
• Partial sum
• sijxixj-1xj (nji1)
• yn sn1 xnxn-1x1
• yn-1 sn-11 xn-1xn-1x1
• y2 s21 x2x1
• y1 s11 x1

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Binary addition as a PPP
Addends
Sum
Carry generation signals
Carry propagation signals
Carry bits
Sum bits
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Binary Addition as a PPP
Block carry generation signal
Block carry propagation signal
Introducing (P,G) operator
The calculation of (P,G) pairs becomes a prefix
problem
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Parallel Prefix Adder

• The General Prefix Adder Structure

Single bit (g,p) generator
Feed through node
Group (G,P) operator
Final sum calculator
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Prefix Adder Graph Representation

• strictly leveled directed acyclic graph (DAG) of
  n columns
• Size number of computation (black) nodes
• Depth level of the latest output

Serial Prefix Circuit
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Prefix Adders Conditional Sum Adder
8 7 6 5 4 3 2 1
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Prefix Adders size and depth

• Objective
• Minimize of nodes, sc(n).
• Minimize depth, dc(n)
• Tradeoff between size and depth
• Ripple Carry Adder
• sc(8) 7
• dc(8) 7
• total 14
• Conditional Sum Adder
• sc(8) 12
• dc(8) 3
• total 15

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Prefix Adders size and depth

• Minimum size n-1, achieved by prefix adder
• Minimum depth ceil(log(n)), achieved by
  conditional sum adder
• Given depth constraint, what is the minimum size?

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Prefix Adders Conditional Sum Adder
8 7 6 5 4 3 2 1

• alphabetical tree
• Binary tree
• Edges do not cross

• For output yi, there is an alphabetical tree
  covering inputs (xi, xi-1, , x1)

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Prefix Adders Conditional Sum Adder
8 7 6 5 4 3 2 1

• The nodes in this tree can be reduced to
• (g, p) o c gpc

• From input x1, there is a tree covering all
  outputs (yi, yi-1, , y1)

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Prefix Adders size and depth

• Theoremsc(n)dnc(n) gt sc(n)dnc(n) gt 2n-2
• dnc(n) means the depth of the last output
• Proof
• Alphabetical tree of yn contains n-1 internal
  nodes.
• For each column where the prefix is not ready,
  at lease one extra node is needed, therefore we
  need at least n-(dnc(n) 1) extra nodes
• sc(n) gtn-1(n(dnc(n)1))2n-2-dnc(n)
• sc(n) dnc(n) gt 2n-2

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Prefix Adders size and depth
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Zero-deficiency/depth-size optimal

• Define the deficiency of a prefix circuit is as
• def size depth (2n 2)
• A prefix circuit is said to be of zero-deficiency
  if its deficiency is zero
• A prefix circuit is said to be depth-size optimal
  if it achieves minimum size under given depth
  requirement

depth-size optimal
Zero-deficiency
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Zero-deficiency/depth-size optimal

• The big picture

What is the minimum depth of zero-deficiency
circuits for a given width?
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Prefix Adders Brent Kung Adder
15 14 13 12 11 10 9 8 7 6 5 4 3
2 1 0

• sc(16) 26
• dc(16) 6
• total 32